VR project 80389901


Direct RF Sampling for Flexible Radio Architectures

Jerzy Dabrowski, Christer Svensson, Håkan Johansson


Objective

The objective of this project is to seek radically new radio front-end architectures with the ultimate goal of full flexibility regarding carrier frequency, bandwidth and noise performance. We aim at fulfilling this objective through a more specific goal of demonstrating a direct sampling RF front-end with high performance and low power consumption to cover a carrier frequency range of 1 - 6 GHz and a broad spectrum of bandwidths. The developed technique should be scalable to higher frequencies in future processes.

Field overview

Radio architectures for various wireless communication applications have developed fast recent years. The observed progress is based on the opportunities offered by modern integrated circuit techniques, particularly the availability of advanced digital signal processing at low power consumption [1-3]. Those digital techniques have facilitated digital modulation, filtering and advanced coding, making wireless communication efficient and mobile. Modern integrated circuits have further led to an increased integration also of the analog radio front-end, including LNAs, mixers, local oscillators, etc. Even though considerable improvements have been achieved, the analog radio front-end has mainly kept its traditional superheterodyne or homodyne architecture that still utilizes analog narrow-band filters, analog mixers, analog phase-shifters, etc. In fact, those components are hard to design, have limited flexibility and require expensive inductors. The traditional radio architectures have a limited flexibility, in that they cover a limited frequency range and a limited number of radio standards. However, communication systems are expected to continue to be heterogeneous which means no common standard will prevail. One can foresee that different operators will continue to deploy different standards in different regions of the world in order to exploit the forces of market to their own profit. On the other hand, few users accept to carry around dedicated terminals for different networks and standards in different areas in the world. These facts have led to the concept of Software Radio (SR), which is a multimode terminal that supports different communication modes in a way that is transparent to the user [4,5]. The idea of SR has achieved much attention recently, resulting in an international forum, which is supposed to accelerate development, deployment, and utilization of software definable radio systems [6]. The traditional approach to implement multimode functionality is to use a custom device for each communication mode, but this is becoming increasingly inefficient both technically and economically [1]. A reasonable alternative is to use an adaptive (flexible) architecture instead, so that the terminal can adapt to the best-suited communication mode under the control of a quality-of-service (QoS) manager. Flexibility is required not only for the digital baseband processing but also for the analog radio frequency (RF) front-end, which should handle a large range of carrier frequencies, possess a flexible bandwidth, and cope with a wide variety of operational conditions. In terms of multimode operation the SR concept has given rise to very tough challenges such as power consumption, terminal size and cost, while keeping up to the performance of dedicated radio hardware (single-mode). Present approaches to SR are based on the idea to convert the RF signal directly to the digital form and next, perform all the signal processing by digital technique. This method is not yet successful, as it puts too high requirements on the AD-converter and also asks for very high performance digital signal processing. Therefore, new alternatives for the RF front-end are sought-after, such as using discrete-time analog signal processing for reducing the sample rate from a value close to the carrier frequency to a value suitable for AD-conversion, without loosing flexibility and signal quality. Appropriate signal filtering can be incorporated in this process as well. Although much research aimed at RF sampling has been done [14-20], a complete direct sampling receiver front-end for multi-standard SR has not been reported so far. Contemporary integrated circuit techniques demonstrate very high speeds also in non-RF style circuits, making our proposal feasible. It has for example been shown that standard industrial techniques of today, such as the well established 0.18?m CMOS, can support data-rates and frequencies of up to 40 GHz [21], and broad-band (inductorless) low noise amplifiers for radio frequencies [22].


Project plan

We propose to continue to exploit direct RF sampling, now complemented with sigma-delta-conversion, as a basis for future flexible radio architectures. Those architectures are expected to be governed by software and to perform mostly digitally, where the RF front-end part is limited to the conversion of the high sample-rate related to the carrier frequency to a lower sample-rate related to the useful (payload) bandwidth. Despite this, the requirements for the RF front-end performance are not diminished. On the contrary, in the future radio the need for tuning to multiple bands and increasingly higher frequencies in combination with very high demands on linearity will impose even harder demands on the frontend. Besides, for the leading edge IC (CMOS) technology, which is optimized for digital applications the circuits based on sampling technique and discrete time processing are better suited than the traditional continuous time RF circuits. In this context, the goal of our project is to demonstrate a direct sampling RF front-end with performance and power consumption comparable to front-ends of today and the additional capability to cover a frequency range of 1 - 6GHz and a broad spectrum of bandwidths. Our solution is to use a broadband or tunable LNA with very high linearity, followed by high speed, linear samplers or mixers. The corresponding output signal after simple filtering is directly converted to digital baseband through a high sampling rate sigma-delta-converter. It is anticipated that the sigma-delta-converter needs digital error correction to meet very high linearity requirements. There are several challenges in this project. The performance demands on radio front-ends are very high, due to the nature of wireless communication. We foresee several problems to meet the requirements. One problem is the linearity that means the 1dB compression point, IP3 and IP2 of whole system must be very high to meet the blocking and intermodulation specifications. This is a tough requirement as a flexible receiver can not utilize very selective RF filters, so the RF frontend must tolerate more interfering signals (blockers) than a traditional receiver. A second problem is the overall frequency planning, where relaxed requirements for RF filters between antenna and the front-end input, are put into perspective [40]. Obviously, here the choice of sampling frequency, including degree of over- or sub-sampling, interleaving, and decimation factor are of primary concern. A third problem is the design and realization of the sigma-delta-converter, and its components, such as integrator, ADC and DAC. The requirement for large dynamic range and high linearity direct a designer toward the first-order, multi-bit sigma-delta-converter, especially when DSP correction is to be employed. The fourth problem is the receiver noise floor, which cannot be compromised with the other specifications. This is really a challenge because the frontend gain must be kept low (for blockers) while the ADC adds its quantization noise. A preliminary research plan is as follows: 1. We will finish the analysis of the latest test chip and perform a critical analysis of the results obtained so far. We expect that the results of this analysis will facilitate the opportunity to specify a new solution with good chances to meet all requirements. 2. Based on this analysis we will develop the various components for a complete front-end meeting all criteria, such as an highly linear and low noise LNA-mixer/sampler accepting large blocker power, a low noise, highly linear, high dynamic range sigma-delta-converter, and appropriate testing techniques. For this purpose we plan to design current mode circuits for which a supply voltage is not a gain limiter. Linearity correction of the sigma-delta-converter by DSP technique will be included, too. 3. As a final proof of the feasibility of our new solution a new version of the prototype receiver will be designed. This design will be based on the results of the most recent analysis, the former prototypes and the new components. It will include the design, fabrication and experimental test of the RF receiver front-end, useful in the carrier frequency range 1-6 GHz, with variable bandwidth, and with a radio performance comparable to traditional (inflexible) solutions. Fabrication will be performed at a commercial silicon vendor.


Results by 2008

We developed a preliminary prototype sampling front-end for 2.4 GHz RF band using 0.18 um CMOS process 2003-2004. The circuit is based on quadrature sampling and it combines three functions, downconversion, low-pass filtering and decimation to low frequency. The design was verified both with a behavioral- and transistor level models [27, 28] and through fabrication followed by experimental measurements [29]. We concluded that work with a plan to develop an advanced discrete-time filtering technique for images and optimization for noise performance. During 2005-2006 we thus developed a second prototype sampling front-end, aimed for the frequency range 2.4-5.6 GHz. This solution includes a wide-band LNA, a downconversion mixer, a new time-discrete low-pass filter and a decimator [30-35]. The prototype chip was designed, fabricated and measured. The wideband LNA was presented at ISSCC in February 2007 [36] and the full chip at a special session at ECCTD in Sept. 2007 [37]. The results from these two demonstrators clearly indicate that the principle of RF sampling is feasible for wide-band and flexible receivers. We also noted that the anti-alias and decimation filters used in these two solutions consume substantial power and deteriorate the receiver noise performance. Therefore a new concept was developed, based on a very high sampling rate sigma-delta converter, making the anti-alias and decimation filter obsolete [38]. A new test chip was developed, based on the previously developed LNA, a new mixer and a new multibit sigma-delta converter including a multi-bit ADC [39] This chip was taped out in October 2007 in 90nm CMOS and sucessfully measured in 2008. Our system studies also demonstrate the need for very high linearity of the whole front-end. For the sigma-delta converter, we expect to solve this problem through digital error correction [38], and for the LNA and mixer linearity the state-of-art solutions don’t meet the requirements of this project, and we are during the course of developing new circuits.

References

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[32] S. Andersson, J. Konopacki, J. Dabrowski, and C. Svensson, "SC Filter for RF Downconversion with Wideband Image Rejection" in Proc. ISCAS 2006, Kos, Greece, May 21-24, 2006 pp. 3542-3545
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