CENIIT project 03.03


Testability-oriented Design Techniques
for Mixed-Signal/ RF Integrated Circuits

Jerzy Dabrowski, PhD, DSc


Project background and industrial relevance

The recent progress in CMOS technology has made it possible to integrate large digital and analog circuits on one chip. For their broad specifications and high sensitivity to process tolerances (e.g. to the transistor size mismatch), especially the mixed-signal/RF circuits require very detailed and long performance tests. To cope with this problem very expensive automatic test equipment (ATE) has been used rather than the techniques known as design-for–testability (DfT) or built-in-self-test (BiST), well established and widely used for digital integrated circuits (ICs). In fact, the resulting high cost of testing has become the main driving force for the research in the field of mixed-signal testability as well as for the respective efforts done by industry, recently.

The DfT and BiST approaches have been proposed to enhance the mixed-signal test process and to reduce the relevant costs whenever possible. In principle, DfT and BiST for mixed-signal and analog/RF circuits are usually patterned after very mature techniques available in the digital domain. Despite this, they usually need individual treatment with respect to the analog nature of a design being developed, the involved specifications (such as DC, AC, distortions, noise), and are subject to the technological process used. As such, the mixed-signal DfT and BiST would accompany designing of the today ICs, and thereby could be considered an open research area, in some sense parallel to (or following) the evolution in ICs design itself.



Project vision

The project plan assumes to develop testability-oriented design techniques for mixed-signal/RF integrated circuits. We would concentrate on systems including transceivers. A system with both transmitter, receiver and an accompanying digital part on the same chip will be used as a platform for our study of testability of mixed-signal systems. In such a case e.g. the analog output can be looped back to the analog input, thus facilitating built-in self-test (BiST). The tests will be aimed at the analog specifications (such as linearity, intermodulation distortions, signal-to-noise ratio) or directly at defects likely to occur on a chip.

The testability of the digital part will only be addressed as much as needed to support the analog tests. Because of complexity of analog specifications the full testability performed by BiST approach can hardly be achieved. Hence, the other design task will be in providing observability and controllability to the circuit under test (CUT) in order to enable or facilitate the tests performed with external equipment.

The proposed research may have significant impact on design methodologies being in use, both theoretically and practically. Theoretically, we hope to formulate advanced behavioral models of mixed-signal functional blocks including the fault option. Those models are also a reasonable way to cope with the problem of designing and testability (jointly DfT/BiST) of complex mixed-signal systems. The fault option should provide an efficient way to develop and verify the test stimulus needed in production tests. Practically, we also expect to develop and validate DfT and BiST techniques oriented at circuit reconfiguration and sharing the on-chip resources. Combining those techniques with circuit calibration is another important objective. The designed and manufactured chips will serve the purpose of practical verification of those techniques.

The experience gained with the demonstration chips would stimulate our research plans in analog DfT/BiST further on. In particular, the state of the art in analog testability suggests that individual treatment with respect to the architecture of a design may be crucial for the applicability of DfT implementation and chip performance. Hence, based on our primary experience we would move to other practical RF architectures representing different tradeoff in performance, such as spectral efficiency or power efficiency. The functional specifications of those architectures have also different sensitivity for device parameters, noise, or cross-talk. Specifically, failures of different type, compared to our primary demonstrators, might be critical for them. Also different approaches might be needed to combine the test with circuit calibration. With this premise, we would seek for other DfT/BiST solutions, individual or optimized for a given application. This would address our long-term vision of the project.


Present status and results obtained

The project commenced in January 2003. During 2003 - 2005 four MS students have been engaged as well, Lin Li, Thana Kantasuwan, Xiaoqin Sheng (all with Socware) and Javier Gonzalez Bayon, (with Erasmus-Socrates). Their MS thesis projects were aimed at DfT/BiST for integrated RF transceivers. The main objectives were to develop and verify the appropriate test algorithms and to design suitable test blocks for CMOS technology. The students defended their theses during spring 2004 and 2005, respectively. The results they obtained were used in the published papers.

In September 2004 a PhD-student, Rashad Ramzan (graduated from KTH in 2003) joined our group. This PhD position was opened in “Design and Testability for RF CMOS” as a part of the CENIIT 03.03 project. Rashad has contributed to the project with new ideas that we published in the recent papers.

Two other MS students, Muhammad Wasim and Noman Hai (both with Socware program) joined the CENIIT project in September 2005. Their MS projects were focused on CMOS RF design, both at the system- and circuit level. Noman Hai completed his project at Philips Research (NL) as a joint project with LiU/ISY on testing of UWB transceivers.

In Feb.2006 a RF front-end designed for test in 0.13 um CMOS was taped out. The manufactured chip was measured at bench and the primary results have been published successfully 2006/07. To address higher frequencies, up to 6 GHz, the test board had to be redesigned and the chip was measured again.

The collaboration with Philips Semiconductor (since 2007 as NXP) initiated in September 2005 has brought new inspirations, which have resulted in new designs to kick off (both at the system and circuit level). During fall 2006 a related MS project was completed by Mehdi Ghulam (with Socware program).

In January 2007 Shakeel Ahmad joined the group as a PhD student. This position is aimed at mixed-signal/RF integrated circuits design for test. In September 2007 a new MS thesis project aimed at on-chip test for linearity was taken by M.Shuaib (with Socware program).

During 2007 a satisfactory progress has been achieved in BER/SER test techniques, oriented both at increased fault detectability and reduction of test time.

Another demonstration chip (flexible receiver front-end/DfT in 90 nm CMOS process) has been designed in 2007 and sucessfully measured in 2008. This chip is provided with new test circuitry, in particular to facilitate on-chip test for linearity.

Our research results and experience gained in the field have been recognized abroad. Specifically, beginning from April 2007 Jerzy Dabrowski was invited for regular lectures on RF DfT delivered within Executive Master in Microelectronics program at ENSICAEN, Caen, France.

The main results obtained in the project comprise the following:

The addressed issues cover both the system- and circuit-level test perspective for RF integrated circuits. The results obtained are unique and we believe they pave a way for new test practices to be introduced by industry.



Publications (2003-08)