Institutionen för systemteknik (ISY)

A programmable radio baseband signal processor is one of the essential enablers of software-defined radio. As wireless standards evolve, the processing power needed for baseband processing increases dramatically and the underlying hardware needs to cope with various standards or even simultaneously maintaining several radio links. Meanwhile, the maximum power consumption allowed by mobile terminals is still strictly limited. These challenges require both system and architecture level innovations. This article introduces a design methodology for radio baseband processors discussing the challenges and solutions of radio baseband signal processing. The LeoCore architecture is presented here as an example of a baseband processor design aimed at reducing power and silicon cost while maintaining sufficient flexibility.

3G evolution towards HSPA and LTE is ongoing which will substantially increase the throughput with higher spectral efficiency. This paper presents the system architecture of an LTE modem based on a programmable baseband processor. The architecture includes a baseband processor that handles processing such as time and frequency synchronization, IFFT/FFT (up to 2048-p), channel estimation and subcarrier demapping. The throughput and latency requirements of a Category 4 User Equipment (CAT4 UE) is met by adding a MIMO symbol detector and a parallel Turbo decoder supporting H-ARQ. This brings both low silicon cost and enough flexibility to support other wireless standards. The complexity demonstrated by the modem shows the practicality and advantage of using programmable baseband processors for a single-chip LTE solution.

Programmability will be increasingly important in futuremulti-standard radio systems. We are proposing an architecturefor fully programmable baseband processing,based on a programmable DSP processor and a numberof configurable accelerators which communicate viaa configurable network. Acceleration of common cycleconsumingDSP jobs is necessary in order to managewide-band modulation schemes. In this paper we investigatewhich jobs are suitable for acceleration in a programmablebaseband processor supporting a number ofcommon Wireless LAN and 3G standards. Benchmarkingshow that with the proposed set of accelerators, ourarchitecture can support the discussed standards, includingIEEE 802.11a 54 Mbit/s wireless LAN reception, at aclock frequency not exceeding 120 MHz.

Programmability will be increasingly important in future multi-standard radio systems. We are presenting a fully programmable and flexible DSP platform capable of efficiently performing channel estimation and Maximum Ratio Combining (MRC) based channel equalization for a large number of wireless transmission systems in software. Our processor is based on a programmable DSP processor with SIMD-computing clusters. We also map Rake receiver kernel functions supporting a large number of commonWireless LAN and 3G standards to this microarchitecture. The use of the inherit flexibility for future standards is also discussed. Benchmarking show that with the proposed instruction set architecture, our architecture can support channel estimation, equalization and decoding of: WCDMA (FDD/TDD-modes), TD-SCDMA and the higher data rates of IEEE 802.11b (CCK) at clock frequency not exceeding 76 MHz.

Programmability will be increasingly important in future multi-standard radio systems. We are proposing an archi tecture for fully programmable baseband processing, based on a programmable DSP processor and a number of config urable accelerators which communicate via a configurable network. Acceleration of common cycle-consuming DSP jobs is necessary in order to manage wide-band modula tion schemes. In this paper we investigate which jobs are suitable for acceleration in a programmable baseband proc sessor supporting a number of common Wireless LAN and 3G standards. Simulations show that with the proposed set of accelerators, our architecture can support the discussed standards, including IEEE 802.11a 54 Mbit/s wireless LAN reception, at a clock frequency not exceeding 120 MHz.

Efficient programmable baseband processors are important to enable true multi-standard radio platforms as convergence of mobile communication devices and systems requires multi-standard processing devices. The processors do not only need the capability to handle differences in a single standard, often there is a great need to cover several completely different modulation methods such as OFDM and CDMA with the same processing device. Programmability can also be used to quickly adapt to new and updated standards within the ever changing wireless communication industry since a pure ASIC solution will not be flexible enough. ASIC solutions for multi-standard baseband processing are also less area efficient than their programmable counterparts since processing resources cannot be efficiently shared between different operations. However, as baseband processing is computationally demanding, traditional DSP architectures cannot be used due to their limited computing capacity. Instead VLIW- and SIMD-based processors are used to provide sufficient computing capacity for baseband applications. The drawback of VLIW-based DSPs is their low power efficiency due to the wide instructions that need to be fetched every clock cycle and their control-path overhead. On the other hand, pure SIMD-based DSPs lack the possibility to perform different concurrent operations. Since memory access power is the dominating part of the power consumption in a processor, other alternatives should be investigated.

In this dissertation a new and unique type of processor architecture has been designed that instead of using the traditional architectures has started from the application requirements with efficiency in mind. The architecture is named ``Single Instruction stream Multiple Tasks'', SIMT in short. The SIMT architecture uses the vector nature of most baseband programs to provide a good trade-off between the flexibility of a VLIW processor and the processing efficiency of a SIMD processor. The contributions of this project are the design and research of key architectural components in the SIMT architecture as well as development of design methodologies. Methodologies for accelerator selection are also presented. Furthermore data dependency control and memory management are studied. Architecture and performance characteristics have also been compared between the SIMT and more traditional processor architectures.

A complete system is demonstrated by the BBP2 baseband processor that has been designed using SIMT technology. The SIMT principle has previously been proven in a small scale in silicon in the BBP1 processor implementing a Wireless LAN transceiver. The second demonstrator chip (BBP2) was manufactured early 2007 and implements a full scale system with multiple SIMD clusters and a controller core supporting multiple threads. It includes enough memory to run symbol processing of DVB-H/T, WiMAX, IEEE 802.11a/b/g and WCDMA, and the silicon area is 11 mm2 in a 0.12 um CMOS technology.