Department of Electrical Engineering (ISY)

Doubly resistively terminated LC filters are optimal from an element sensitivity point of view and are therefore used as reference filter for high-performance active filters. The later inherits the sensitivity properties of the LC filter. Hence it is important to design the reference filter to have minimal element sensitivity. In this paper, we first review the mechanism for the low sensitivity and give an upper bound on the deviation in the passband attenuation. Next we compare classical lowpass approximations with respect to their influence on the sensitivity and propose the use of diminishing ripple in the passband to further reduce the sensitivity. Finally, we propose a design strategy for doubly resistively terminated LC filters with low sensitivity.

An asynchronous wrapper with novel handshake circuits for data communication in globally asynchronous locally synchronous (GALS) systems is proposed. The handshake circuits include two communication ports and a local clock generator. Two approaches for the implementation of communication ports are presented, one with pure standard cells and the others with Muller-C elements. The detailed design methodology for GALS systems is given and the circuits are validated with VHDL and circuits simulation in standard CMOS technology

In this work filter structures that decrease the required number of multipliers and adders for implementation of linear-phase FIR filters using frequency-response masking techniques are introduced. The basic idea of the proposed structures is that identical subfilters are used. This leads to the same arithmetic structure can be multiplexed in the implementation, reducing the number of required multipliers and adders. The subfilters are mapped using the folding transformation to obtain an area-efficient time-multiplexed (or pipeline/interleaved) implementation. Both narrow-band and wide-band frequency-response masking as well as arbitrary bandwidth frequency-response masking techniques are considered. The filter design is discussed and for each filter structure the limits on the specifications are derived. Designed examples show the usefulness of the proposed structures.

This paper introduces new tree-structured uniform-band and octave-band digital filter banks (FBs). These FBs make use of half-band IIR filters in the analysis FBs and FIR filters in the synthesis FBs. The resulting FBs are asymmetric in the sense that the analysis FB has a very low arithmetic complexity whereas that in the synthesis FB is higher. However, compared with other asymmetric FBs, the proposed ones have in many cases a lower overall arithmetic complexity and delay. The proposed FBs have magnitude distortion but no phase distortion, further, the aliasing components are either zero (uniform-band case) or approximately zero (octave-band case). The FBs are designed using linear and nonlinear programming. Design examples are included demonstrating the properties of the proposed filters banks. ⌐ 2003 Published by Elsevier B.V.

In this work, a new algorithm called nonrecursive signed common subexpression elimination (NR-SCSE) is discussed, and several Applications in the area of multiplierless finite-impulse response (FIR) filters are developed. While the recursive utilization of a common subexpression generates a high logic depth into the digital structure, the NR-SCSE algorithm allows the designer to overcome this problem by using each subexpression once. The paper presents a complete description of the algorithm, and a comparison with two other well-known options: the graph synthesis, and the classical common subexpression elimination technique. Main results show that the NR-SCSE implementations of several benchmark circuits offer the best relation between occupied area and logic depth respect to the previous values published in the technical literature.

The frequency-response masking approach for high-speed recursive infinite-impulse response (IIR) digital filters is introduced. In this approach, the overall filter consists of a periodic model filter, its power-complementary periodic filter, and two masking filters. The model filters are composed of two all-pass filters in parallel, whereas the masking filters are linear-phase finite-impulse response (FIR) filters. The transfer functions of the all-pass filters are functions of zM, which implies that the maximal sample frequency for the overall filter is M times that of the corresponding conventional IIR filter. The maximal sample frequency can be increased to an arbitrary level for arbitrary bandwidths. The overall filter can be designed by separately optimizing the model and masking filters with the aid of conventional approximation techniques. The obtained overall filter also serves as a good initial filter for further optimization. Both nonlinear-phase and approximately linear-phase filters are considered. By using the new approach, the potential problems of pole-zero cancellations, which are inherent in algorithm transformation techniques, are avoided. Further, robust filters under finite-arithmetic conditions can always be obtained by using wave-digital all-pass filters and non-recursive FIR filters. Several design examples are included illustrating the properties of the new filters.

Wave digital filter (WDF) structures for high-speed narrow-band and wide-band filtering are introduced. The narrow-band filter is composed of a periodic model filter and one or several, possibly periodic, masking filters in cascade. Lattice and bireciprocal lattice WDF filters are used for the model and masking filters, respectively. The wide-band filter consists of a narrow-band filter in parallel with an all-pass filter. The overall filters can be designed by separately designing the model and masking filters. The filters obtained in this approach also serve as good initial filters for further optimization. Both nonlinear and approximately linear phase filters are considered. One major advantage of the new filters over the corresponding conventional filters is that they have a substantially higher maximal sample frequency. In the case of approximately linear phase, the computational complexity can also be reduced. Further, the use of bireciprocal lattice wave digital (WD) masking filters also makes it possible to reduce the complexity, compared with the case in which FIR masking filters are used. Several design examples and a discussion of finite wordlength effects are included for demonstrating the properties of the new filters.

An on-chip clock for frequencies up to 190 MHz is presented. This clock generator can be used for application specific digital signal processors which are clocked faster than the off-chip system clock. It is useful for both processors with a few cycles per sample or for high frequency bit-serial processors which need a large number of cycles.

General‐purpose DSP processors, application‐specific processors, and algorithm‐specific processors are used to implement different types of DSP systems or subsystems. They are typically used in applications involving complex and irregular algorithms while application‐specific processors provide lower unit cost and higher performance for a specific application, particularly when the volume of production is high. Most DSP applications use fractional arithmetic instead of integer arithmetic. Multimedia and communication applications involve real‐time audio and video/image processing which very often require sum‐of‐products (SOP) computation. The need of computing non‐linear functions arises in many different applications. The straightforward method of approximating an elementary function is to just store the values in a look‐up table typically leads to large tables, even though the resulting area from standard cell synthesis grows slower than the number of memory bits. It is of interest to find ways to approximate elementary functions using a trade‐off between arithmetic operations and look‐up tables.

In this work we discuss the realization of constant multiplication using a minimum number of carry-save adders. We consider both non-redundant and carry-save representation for the input data. For both cases we present all possible interconnection topologies, using up to six and five adders, respectively. These are sufficient to realize constant multiplications for all coefficients with a wordlength up to 19 bits.

In this work modelling of the power consumption for ripple-carry adders implemented in CMOS is considered. Based on the switching activity of each input bit, two switching models, one full and one simplified, are derived. These switching models can be used to derive the average energy consumed for one computation. This work extends previous results by introducing a data dependent power model, i.e., correlated input data is considered. Examples show that the switching model is accurate, while there are some differences in the power consumption. This is due to the fact that not all switching in the ripple-carry adder is rail-to-rail (full swing) in the actual implementation.

The power modeling of different realizations of cascaded integrator-comb (CIC) decimation filters has been a subject of several recent works. In this work we have extended these with modeling of leakage power, which is an important factor since the input sample rate may differ several orders of magnitude. Furthermore, we have pointed out the importance of the input wordlength on the comparison of recursive and nonrecursive implementations.

In this work we propose a switching activity model for single adder multipliers. This correspond to the case where a signal is added to a shifted version of itself, which is a common part in multiple constant multiplication (MCM). Hence, the proposed model is suitable to be used in power consumption aware MCM algorithms. The model is shown to agree well with simulations, and for the studied test cases a maximum error of 0.26% is obtained.

Implementation of FIR filters using shift-and-add multipliers has been an active research area for the last decade. However, almost all algorithms so far has been focused on reducing the number of adders and subtractors, while little effort was put on the bit-level implementation. In this work we propose a method to optimize the number of full adders and half adders required to realize a given number of additions. We present results which show that both area and power consumption can be reduced using the proposed method.

Computations in logarithmic number systems require realizations of four different elementary functions. In this work we utilize a recently proposed approximation method based on weighted sums of bit-products to realize these functions. It is shown that the considered method can be used to efficiently realize the different functions. However, a transformation is proposed to improve the results for functions with logarithmic characteristics.

Multiple constant multiplication (MCM), i.e., realizing a number of constant multiplications using a minimum number of adders and subtracters, has been an active research area for the last decade. Almost all work has been focused on single rate FIR filters. However, for polyphase interpolation and decimation FIR filters there are two different implementation alternatives. For interpolation, direct form subfilters lead to fewer registers as they can be shared among the subfilters. The arithmetic part corresponds to a matrix vector multiplication. Using transposed direct form subfilters, the registers can not be shared, while the arithmetic part has the same input to all coefficients, and, hence, the redundancy between the coefficients is expected to be higher. For decimation filters the opposite holds for direct form and transposed direct form subfilters. In this work we discuss the trade-off between adders/subtracters and registers, and present implementation results for area, speed, and power for different realizations

In this work a novel approach for approximating elementary functions is presented. By rewriting the function as a sum of weighted bit-products an efficient implementation is obtained. For most functions a majority of the bit-products can be neglected and still obtain good accuracy. The method is suitable for high-speed implementation of fixed-point functions.

In this paper trade-offs in multiplier blocks are studied.Three different algorithms for realization of multiplierblocks are compared in terms of complexity, logic depth,and power consumption. A new algorithm that reduces thenumber of shifts while the number of adders is on averagethe same is presented. Hence, the total complexity is reduced for multiplier blocks implemented using serialarithmetic, where shift operations has a cost. The design oflow power multiplier blocks is shown to be a more complicated problem than to reduce the complexity. A mainfactor that need to be considered is logic depth.

An angle rotation based approach to simultaneously compute sin(x) and cos(x) is presented. The approach yields a weighted sum of bit-products of the binary bits that represent the angle x. We discuss the required number of terms in the polynomial as well as the required coefficient wordlength as function of accuracy. The approach yields a combinatorial realization with a low complexity. We also propose a corresponding fast and simple architecture. The combinatorial circuit has low latency and can easily be pipelined for a high throughput.

Recently, a novel technique to compute sine and cosine has been proposed. By rewriting the expressions using trigonometric equations a weighted sum of bit-products is used to compute the values. This can then be mapped onto a bit-product generator followed by an adder tree. This provides an efficient architecture that can be pipelined to an arbitrary degree. It was shown in previous work that it is possible to remove a large portion of the bit-products and still obtain accurate results. The objective of this work is to study the effects of this removal and also the finite wordlength representation of the weights. Furthermore, optimization problems are formulated that can be used to minimize the maximum absolute error, the average absolute error, and the mean square error for the output values, respectively, as well as implementation complexity under error constraints.

Recently, a noveltechnique to compute sine and cosine has been proposed. Byrewriting the expressions using trigonometric equations a weightedsum of bit-products are used to compute the values. This can thenbe mapped onto a bit-product generator followed by an adder tree.This provides an efficient architecture that can be pipelined to anarbitrary degree. It was shown in previous work that it is possibleto remove a large portion of the bit-products and still obtainaccurate results. The effects of this removal and also the finiteworldlength representation of the weights has also been discussedin previous work. The objective of this work is to study differentways to split the architecture into sub-blocks that may be disabledto decrease the power consumption.

Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we propose an architecture for an early decision decoding algorithm. The algorithm significantly reduces the number of memory accesses. Simulation results show that the increased energy dissipation of the components is small compared to the reduced dissipation of the memories.

Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we investigate a modification to the decoding algorithm, using early decisions for bits with high reliabilities. This reduces the amount of messages passed by the algorithm, which can be expected to reduce the switching activity of a hardware implementation. While direct application of the modification results in severe performance penalties, we show how to adapt the algorithm to reduce the impact, resulting in a negligible decrease in error correction performance.

Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we investigate a modification to the decoding algorithm, using early decisions for bits with high reliabilities. Currently, there are two early decision schemes proposed. We compare their theoretical performances and their suitability for hardware implementation. We also propose a new decision method, which we call weak decisions, that offers an increase in performance by a factor of two.

In this paper, we propose a VLSI implementation method for one-dimensional discrete wavelet transform (1D-DWT) filter bank based on the GALS systems approach. An asynchronous wrapper, which includes two data communication ports and a local clock controller, is designed for the asynchronous data communication between the locally synchronous filtering modules in the wavelet filter bank. The detailed design methodology for the GALS architecture of ID-DWT filter bank is presented, and the circuits are validated with VHDL and implemented with standard CMOS technology.

In this work a model for estimation of the power consumption in bit-serial, constant coefficient multipliers is presented. The multipliers are implemented using shift-add operations. Model parameters for the required components, i.e., flip-flops and full-adders, are derived. The power for a multiplier is obtained by summing the power for all components included in the corresponding network of shifts and adders.

In this work a mixed integer linear programming (MILP) formulation for the design of a class of linear-phase FIR filters are presented. The formulation can be solved using general purpose MILP solvers to obtain filter implementationwith a minimum number of signed-power-of-two (SPT) terms given a filter specification. The filter structures considered are based on reduced complexity polyphase decomposition. It is shown that the total number of SPT terms per sample can be reduced using this filter architecture. However, the savings are not as large as other work propose, when optimal design techniques are used.

In this paper we propose a method for implementation of sum-of-products using a shifted permuted difference coefficient method. Here we focus on implementation of FIR filters but the method is generally applicable to computation of sum-of-products. In this work we identify two fundamental blocks in the difference coefficient structure, a permutation network and an adder network. The former determine how the difference coefficients are selected while the latter computes the differences. We also propose that the differences are computed on odd, integer coefficients only. The proposed method is fast and yields filter implementations with low arithmetic complexity. This makes it a good candidate for being incorporated into the search for quantized coefficients in the synthesis of FIR filters.

In this paper a method for computing the switching activity in bit-serial constant-coefficient multipliers is presented. The multipliers are described using a graph representation. It is shown that the average switching activity in all multipliers with up to four adders can be determined. Most of the switching activities can be obtained directly from the derived formulas and the remaining by using look-up tables. The switching activities are useful to estimate the power consumption, and makes it possible to choose the best power saving multiplier structure.

In this paper an algorithm for realization of multiplier blocks using bitand digit-serial arithmetic is presented. Previously presented algorithms were designed for bit-parallel arithmetic and for that reason assumed no cost for shifts. It is shown that the new algorithm reduces the total complexity significantly.

Recently, a novel technique for the multiple constant multiplication (MCM) problem using minimum spanning trees (MSTs) has been proposed. The approach works by finding simple differences between the coefficients to realize and then applying the same method to the differences (which is an MCM problem as well). Each iteration is divided into two steps. First, finding a minimum spanning tree in the graph describing the differences between the coefficients. Second, as each edge in the graph may correspond to more than one difference, one difference is selected for each edge in the MST. Generally, both these stages have multiple solutions. The aim of this work is to more closely study how the MST and the differences should be selected to give better total results. It is also discussed how the two stages in each iteration may be joined into one problem.

In this work we formulate a mixed integer linear programming (MILP) problem that minimizes the number of signed-power-of- two (SPT) terms given a filter specification for linear-phase frequency-response masking (FRM) filters. The proposed method designs the filters in two steps. The model filter and the masking filters are designed separately, but subject to each other. Hence, it is not guaranteed that the global minimum is obtained. However, each solution is optimal given the other filter(s), and iteration may improve the overall solution. The filter design problems are formulated using normalized peak ripple magnitude (NPRM), which for FRM filters introduces some implications, which is also discussed in this work.

By introducing simplifications to multiplier graphs we extend the previous work on minimum adder multipliers to five adders and show that this is enough to express all coefficients up to 19 bits. The average savings are more than 25% for 19 bits compared with CSD multipliers. The simplifications include addition reordering and vertex reduction to see that different graphs can generate the same coefficient sets. Thus, fewer graphs need to be evaluated. A classification of the graphs reduces the effort to search the coefficient space further.

In this work, we introduce a novel approach to digit-serial/parallel multiplication. This general class of multipliers is based on shift-accumulation which also makes the approach suitable for implementation of shift-accumulators in distributed arithmetic. As a variable in the design process, the maximal number of cascaded full-adders can be selected. Thus, it is possible to, as a special case, obtain a bit-level pipelined multiplier. Both general and fixed coefficient multiplication is considered. The hardware complexity is low compared with other approaches.

In this work we formulate a mixed integer linear programming (MILP) problem for designing linear-phase FIR filters with low arithmetic complexity. By incorporating subexpression sharing in the problem formulation, the number of adders will be lower compared with previous approaches, where minimizing the number of non-zero bits of the coefficients has been the objective.

Pipeline-interleaving is an implementation method yielding a reduced area. This paper discusses the power consumption for such implementations, compared to a direct implementation. An examplefilter has been implemented, both as a direct structure and a pipeline-interleaved structure, and the results show a 38% and 23% increase in power consumption for correlated and uncorrelated input data respectively using a pipeline-interleaved structure. Possible explanations of the results are discussed for the example filter.

A new class oftwo-channel IIR/FIR filter banks was introduced by the authors in2000 with half-band IIR analysis filters and FIR synthesis filters.This type of filter bank features very low-complexity analysisfilters and simultaneously a low overall complexity. In this paper,we consider finite-wordlength effects of these filterbanks

A class of tree-structured octave-band digital filter banks is introduced. The filter banks make use of half-band IIR filters in the analysis bank and FIR filters in the synthesis bank which results in very low-complexity analysis filters. Further, the overall complexity is lower than, or comparable to, that of conventional filter banks. The overall filter banks approximate perfect reconstruction in the following sense. The distortion function is a linear-phase function approximating one in magnitude whereas the aliasing terms approximate zero. The filter banks are designed using linear and nonlinear programming. Design examples are included demonstrating the properties of the new filter banks

The number of multiplications has been a key merit for FFT algorithms. It has important impact on the total power consumption. In this paper, we present a 16-point FFT module, which reduc-es the multiplicative complexity by using real constant multiplications. A pipeline FFT proces-sor has been implemented with the 16-point module and simulation result shows that it is an attractive candidate to reduce the power consumption.

A class of digital filter banks is introduced, in which the anal-ysis filters are half band IIR filters and the synthesis filters are FIR filters. The proposed filter bank satisfy approximately perfect reconstruction and has an exact linear phase. Further, it is suitable for applications where a very low complexity analysis filter bank is required. 1 INTRODUCTION This paper introduces a class of two-channel digital filter banks. This class belongs to the general class of two-channel maximally decimated filter banks shown in Fig. 1. It consists of an analysis filter bank, formed by the analysis filters H 0 (z) and H 1 (z), and a synthesis filter bank, formed by the synthesis filters G 0 (z) and G 1 (z). Downsamplers and upsamplers are present between the analysis and synthesis filter banks in order to reduce the computational workload. In the filter banks that have been proposed during the past decades, the analysis and synthesis filters have equal complexities [1], [2]. This holds true for both IIR and FIR filter banks. In this paper, we propose a filter bank in which the analy-sis filters are half-band IIR filters whereas the synthesis filters are FIR filters. The complexity of the analysis filter bank is then very low whereas that of the synthesis filter bank is higher. However, the overall complexity is comparable to that of conventional filter banks. Such filter banks are of interest in applications where it is important to have a very low com-plexity for the analysis filter bank, and where one can afford a higher complexity in the synthesis filter bank. One is mixed discrete-time and digital filter banks for A/D-conversion, where the analysis filters are discrete-time filters, such as SC-filters. Here filter banks are used to reduce the distortion caused by gain-and phase mismatch errors which is inherent in parallel A/D converters. Since it is more difficult to imple-ment high-resolution discrete-time filters than digital filters, it is essential to use low-order analysis filters. The proposed class of filter banks are approximately per-fect reconstruction filter banks. They have magnitude distor-tion, but no phase distortion. Further, the aliasing can be made either exactly zero or approximately zero. In this paper we only consider the case in which the analysis filters have low complexity. Naturally, it is possible to let the synthesis filters be the low-complexity filters by simply interchanging the analysis and synthesis filters.

This paper introduces hybrid analog/digital filter banks with alias-free subbands. The aliasing at the output is small due to stopband attenuation of the individual filters and not due to cancellation, which is the case in maximally decimated filter banks. Thus, the accuracy requirements of the analog filter components are relaxed

A program for manual scheduling of digital signal processing algorithms is presented. The program works with a cyclic scheduling formulation that yield maximally fast implementations. The operations can be moved across a number of sample intervals by drag-and-drop-operations. By implementing the program in Java it can be used on all platforms supporting Java.

High-speed recursive digital filters are of interest for applications focusing on high-speed as well as low power consumption because excess speed can be traded for low power consumption through the use of power supply voltage scaling techniques. This paper gives an overview of high-speed recursive digital filters based on frequency masking techniques.

In this paper a design procedure for 2-channel hybrid filter banks for use in high-speed A/D converters is proposed. By using minimax optimization, A/D converting systems consisting of an analog analysis filter bank and a digital synthesis filter bank are designed with the aid of bireciprocal lattice wave digital filters. Using hybrid filter banks the requirements on the A/D converters used in each channel are reduced. The performance of the resulting system when simultaneously introducing gain and phase errors due to mismatches between the A/D converters and sample time uncertainty in the sample-and-hold circuits, respectively, is analysed by means of the expected attenuation of the resulting aliasing components

This paper introduces a class of hybrid analog/digital filter banks with approximately perfect magnitude reconstruction. The filter bank consists of analog analysis and digital synthesis filter banks. The analog analysis filters are formed as a sum and difference of two allpass subfilters, respectively, resulting in filters with low orders and few free parameters, which is advantageous from implementation and design points of view. The digital synthesis filters are odd-order linear-phase FIR filters with symmetric and anti-symmetric impulse responses, respectively. The filter design is performed by first optimizing the analog analysis filters. Then, with the analog filters fixed, optimum digital synthesis filters, in the minimax sense, are obtained with the aid of linear programming

Recently, a filter structure for narrow-band filtering based on lattice wave digital filters was introduced. The structure has increased parallelism over the corresponding direct realization. In this paper, hardware implementation of the filter structure is discussed. The suggested approach uses bit-serial processing elements that are scheduled so that a maximally fast implementation is achieved. An example is given where our implementation approach increases the sample frequency by a factor of 4 compared to a direct realization.

We propose an efficient scheme for implementing a complex multiplier based on distributed arithmetic. A modified bit-serial shift-accumulator for distributed arithmetic is also proposed for computing a*b+c, where a, b and c are complex numbers. The shift-accumulator is highly regular and modular and consists of only three types of bit-slices, each of which consists of only three types of blocks, multiplexers, exclusive OR gates, and latches. The implementation is done using a robust differential single-phase clocked logic style suitable for high-speed and low power operation. The resulting implementation of the complex multiplier has a maximum clock frequency of 250 MHz, consumes 70 mW, and occupies a chip area of 0.5 mm² in a double-metal 0.8 μm process. The coefficient word length and the data word length are 12 bits and 16 bits, respectively

In this paper two bit-serial carry save adders are implemented using a recently proposed differential logic style. The clocking scheme uses a single clock phase with non-precharged stages of logic that may be merged with the latches or the flip-flops. A novel flip-flop structure is used in one of the adders, which significantly lowers the number of clocked transistors. The logic style used in the adder realizations suits high speed and low power operation in both bit-serial and bit-parallel implementations, since all logic nets are purely in NMOS. The logic style is also robust for clock slope and yields a data noise margin equal to Vdd/2. The adders reached a maximal clock frequency of 300 MHz in a 0.8 mm process with a 3.0 V power supply voltage.

Bit-serial arithmetic is often advantageous both in terms of small chip area and low power consumption. When using bit-serial arithmetic for implementation of recursive digital filters, the maximal sample frequency is inversely proportional to the coefficient word lengths of the filters. For high-speed applications it is therefore essential to find filter structures with short coefficients. One way to do this is to use cascaded low-order filters instead of one high-order filter. Problems arise though when the cascaded filters are to be used for interpolation and decimation, since the straightforward realization increases the workload due to the different sample rates involved. However, we have developed a novel realization technique which keep the workload at a minimum with the additional possibility to use a high sample frequency. A digital filter for both interpolation and decimation, realized using this novel technique applied on two cascaded lattice wave digital filters, has been implemented. The filter can be used for sample rate conversions between 25 and 50 MHz.

A SIC architecture with asynchronous bit-serial PEs is presented and applied to the Sande-Tukey's FFT. The resulting architecture can easily be modified for higher throughput and/or lower power consumption. Using this architecture a high-performance chip for use in an OFDM transmission system has been designed.

An approach to schedule lattice wave digital filters so that the maximal sample frequency is obtained is presented. In the approach, bit-serial arithmetic and a scheduling method that decouples the sample period from the scheduling period are used. A lower bound on the scheduling period required to arrive at the minimum sample period is given. Different latency models for the arithmetic operations, and their effect on the minimum sample period are discussed. The operation schedule is mapped to a hardware structure using isomorphic mapping. The throughput of the resulting implementations is comparable to corresponding bit-parallel implementations.

An approach to schedule lattice wave digital filters so that the maximal sample frequency is obtained is presented. In the approach, bit-serial arithmetic and a scheduling method that decouples the sample period from the scheduling period are used. A lower bound on the scheduling period required to arrive at the minimum sample period is given. Different latency models for the arithmetic operations, and their effect on the minimum sample period are discussed. The operation schedule is mapped to a hardware structure using isomorphic mapping. The throughput of the resulting implementations is comparable to corresponding bit-parallel implementations.

In this paper we show that it is not sufficient to specify the latency of the processing elements without considering the throughput to arrive at a maximally fast implementation of a recursive algorithm. This result is due to the observation that the latency for serial multiplication actually is dependent on the throughput. We demonstrate how higher throughput is obtained for a first-order recursive filter by increasing the latency of the processing elements. Three models for the latency are examined from corresponding implementations of the filter. For one of the models, canonic signed-digit coding of the coefficient is used which results in a significant increase of the throughput of a serial/parallel multiplier.

A new scheduling formulation for data independent recursive algorithms is proposed. This formulation is intuitive and finds a static rate optimal schedules. Processing elements may be non-preemptive and non-homogenous. Comparison with some other common scheduling methods to increase throughput is made.

A multirate IF filter for mobile radio has been implemented in silicon. The filter consists of a decimation stage followed by a bandpass filter. Both parts use a lattice wave digital structure. The design and implementation are described beginning with the filter specification and proceed through algorithmic design, operations scheduling, and resource allocation and assignment. Every step tries to minimize the amount of resources in the final implementation, thereby reducing power consumption. Finally the architecture is selected and the system is described using synthesizable VHDL in order to arrive at a chip layout using standard-cell technology. This design technique is used to reduce the design work.

In this paper we discuss the design and implementation of fixed-function, recursive DSP algorithms. We demonstrate by means of a wave digital lattice filter that a sampling frequency of more than 130 MHz can be achieved for a recursive algorithm by using bit-serial arithmetic. The proposed approach leads to very fast recursive algorithms with low power consumption and a minimum requirement of chip area. Further, we show that the iteration period bound by Renfors et al. often can be lowered by applying numerical equivalence transformations to the signal-flow graph. The proposed implementation technique can easily be extended to higher-order bireciprocal and non-bireciprocal lattice filters as well as other types of DSP algorithms.

A custom DSP chip for mobile radio systems like the American IS-54 system is presented. The application is a digital intermediate frequency filter which is intended to replace expensive analog filters. It is a lattice wave digital filter with fixed coefficient bit-serial arithmetic. A technique which is useful for area efficient layouts in high throughput real time signal processing is discussed.

In this paper we discuss the implementation of maximally fast fixed-function digital filters. We demonstrate by means of an example that digital filters with sampling frequencies of more than hundred MHz can efficiently be implemented by using bit-serial PEs. The proposed approach lead to maximally fast filters that require little chip area and have low power consumption. Further, we show that the iteration period bound by Renfors et al. often can be lowered by applying equivalence transformations to the signal-flow graph.