We present the design of an integrated multiplexer and a dc clamp for the input analog interface of a high-speed video digitizer in the 1.1-V 65-nm complementary metal-oxide-semiconductor process. The ac-coupled video signal is dc restored using a novel all-digital current-mode charge pump. An eight-input multiplexer is realized with T-switches, each containing two series-connected bootstrapped switches. A T-switchs grounding branch is merged with the pull-down end of the clamping charge pump. An adaptive digital feedback loop encompassing a video analog-to-digital converter (ADC) controls the clamp charge pump. The bootstrapped switches have been adapted to suit the video environment, allowing on-the-fly recharging. The varying ON-resistance of the conventional bootstrapped switch is utilized to linearize the multiplexer response by canceling the effect of the nonlinear load capacitance contributed by the clamp transistors. Under worst case conditions, the multiplexer maintains a 62-85-dB spurious-free dynamic range over a range of known input video frequencies, and it reduces the second-order harmonic component upon optimization. The dc clamp provides 12-bit precision over the full range of the video ADC and can set the dc at the target level for at most 194 video lines.

In this brief, we propose how the hardware complexity of arbitrary-order digital multibit error-feedback delta-sigma modulators can be reduced. This is achieved by splitting the combinatorial circuitry of the modulators into two parts, i.e., one producing the modulator output and another producing the error signal fed back. The part producing modulator output is removed by utilizing a unit-element-based digital-to-analog converter. To illustrate the reduced complexity and power consumption, we compare the synthesized results with those of conventional structures. Fourth-order modulators implemented with the proposed technique use up to 26% less area compared with conventional implementations. Due to the area reduction, the designs consume up to 33% less dynamic power. Furthermore, it can operate at a frequency 100 MHz higher than that of the conventional.

This paper introduces add-equalize structures for the implementation of linear-phase Nyquist (th-band) finite-length impulse response (FIR) filter interpolators and decimators. The paper also introduces a systematic design technique for these structures based on iteratively reweighted -norm minimization. In the proposed structures, the polyphase components share common parts which leads to a considerably lower implementation complexity as compared to conventional single-stage converter structures. The complexity is comparable to that of multi-stage Nyquist structures. A main advantage of the proposed structures is that they work equally well for all integer conversion factors, thus including prime numbers which cannot be handled by the regular multi-stage Nyquist converters. Moreover, the paper shows how to utilize the frequency-response masking approach to further reduce the complexity for sharp-transition specifications. It also shows how the proposed structures can be used to reduce the complexity for reconfigurable sampling rate converters. Several design examples are included to demonstrate the effectiveness of the proposed structures.

This paper describes the front-end of a fully integrated analog interface for 300 MSps, high-definition video digitizers in a system on-chip environment. The analog interface is implemented in a 1.2 V, 65-nm digital CMOS process and the design minimizes the number of power domains using core transistors only. Each analog video receiver channel contains an integrated multiplexer with a current-mode dc-clamp, a programmable gain amplifier (PGA) and a pseudo second-order RC low-pass filter. The digital charge-pump clamp is integrated with low-voltage bootstrapped tee-switches inside the multiplexer, while restoring the dc component of ac-coupled inputs. The PGA contains a four-stage fully symmetric pseudo-differential amplifier with common-mode feedforward and inherent common-mode feedback, utilized in a closed loop capacitive feedback configuration. The amplifier features offset cancellation during the horizontal blanking. The video interface is evaluated using a unique test signal over a range of video formats for INL+/DNL+, INL-/DNL-. The 0.07-0.39 mV INL, 2-70 mu V DNL, and 66-74 dB of SFDR, enable us to target various formats for 9-12 bit Low-voltage digitizers.

Logarithmic number system (LNS) is an attractive alternative to realize finite-length impulse response filters because ofmultiplication in the linear domain being only addition in the logarithmic domain. In the literature, linear coefficients are directlyreplaced by the logarithmic equivalent. In this paper, an approach to directly optimize the finite word length coefficients in theLNS domain is proposed. This branch and bound algorithm is implemented based on LNS integers and several different branchingstrategies are proposed and evaluated. Optimal coefficients in the minimax sense are obtained and compared with the traditionalfinite word length representation in the linear domain as well as using rounding. Results show that the proposed method naturallyprovides smaller approximation error compared to rounding. Furthermore, they provide insights into finite word length propertiesof FIR filters coefficients in the LNS domain and show that LNS FIR filters typically provide a better approximation error comparedto a standard FIR filter.

This paper proposes a method for designing high-order linear-phase finite-length impulse response (FIR) filters which are required as, e.g., the prototype filters in filter banks (FBs) and transmultiplexers (TMUXs) with a large number of channels. The proposed method uses the Farrow structure to express the polyphase components of the desired filter. Thereby, the only unknown parameters, in the filter design, are the coefficients of the Farrow subfilters. The number of these unknown parameters is considerably smaller than that of the direct filter design methods. Besides these unknown parameters, the proposed method needs some predefined multipliers. Although the number of these multipliers is larger than the number of unknown parameters, they are known a priori. The proposed method is generally applicable to any linear-phase FIR filter irrespective of its order being high, low, even, or odd as well as the impulse response being symmetric or antisymmetric. However, it is more efficient for filters with high orders as the conventional design of such filters is more challenging. For example, to design a linear-phase FIR lowpass filter of order 131071 with a stopband attenuation of about 55 dB, which is used as the prototype filter of a cosine modulated filter bank (CMFB) with 8192 channels, our proposed method requires only 16 unknown parameters. The paper gives design examples for individual lowpass filters as well as the prototype filters for fixed and flexible modulated FBs.

This paper introduces a class of reconfigurable two-stage Nyquist filters where the Farrow structure realizes the polyphase components of linear-phase finite-length impulse response (FIR) filters. By adjusting the variable predetermined multipliers of the Farrow structure, various linear-phase FIR Nyquist filters and integer interpolation/decimation structures are obtained, online. However, the filter design problem is solved only once, offline. Design examples, based on the reweighted l(1)-norm minimization, illustrate the proposed method. Savings in the arithmetic complexity are obtained when compared to the reconfigurable single-stage structures.

In time-interleaved analog-to-digital converters (TI-ADCs), the timing mismatches between the channels result in a periodically nonuniformly sampled sequence at the output. Such nonuniformly sampled output limits the achievable resolution of the TI-ADC. In order to correct the errors due to timing mismatches, the output of the TI-ADC is passed through a digital time-varying finite-length impulse response reconstructor. Such reconstructors convert the nonuniformly sampled output sequence to a uniformly spaced output. Since the reconstructor runs at the output rate of the TI-ADC, it is beneficial to reduce the number of coefficient multipliers in the reconstructor. Also, it is advantageous to have as few coefficient updates as possible when the timing errors change. Reconstructors that reduce the number of multipliers to be updated online do so at a cost of increased number of multiplications per corrected output sample. This paper proposes a technique which can be used to reduce the number of reconstructor coefficients that need to be updated online without increasing the number of multiplications per corrected output sample.

This paper proposes a method to design variable fractional-delay (FD) filters using the Farrow structure. In the transfer function of the Farrow structure, different subfilters are weighted by different powers of the FD value. As both the FD value and its powers are smaller than 0.5, our proposed method uses them as diminishing weighting functions. The approximation error, for each subfilter, is then increased in proportion to the power of the FD value. This gives a new distribution for the orders of the Farrow subfilters which has not been utilized before. This paper also includes these diminishing weighting functions in the filter design so as to obtain their optimal values, iteratively. We consider subfilters of both even and odd orders. Examples illustrate our proposed method and comparisons, to various earlier designs, show a reduction of the arithmetic complexity.

Despite the outstanding performance of non-binary low-density parity-check (LDPC) codes over many communication channels, they are not in widespread use yet. This is due to the high implementation complexity of their decoding algorithms, even those that compromise performance for the sake of simplicity. less thanbrgreater than less thanbrgreater thanIn this paper, we present three algorithms based on stochastic computation to reduce the decoding complexity. The first is a purely stochastic algorithm with error-correcting performance matching that of the sum-product algorithm (SPA) for LDPC codes over Galois fields with low order and a small variable node degree. We also present a modified version which reduces the number of decoding iterations required while remaining purely stochastic and having a low per-iteration complexity. less thanbrgreater than less thanbrgreater thanThe second algorithm, relaxed half-stochastic (RHS) decoding, combines elements of the SPA and the stochastic decoder and uses successive relaxation to match the error-correcting performance of the SPA. Furthermore, it uses fewer iterations than the purely stochastic algorithm and does not have limitations on the field order and variable node degree of the codes it can decode. less thanbrgreater than less thanbrgreater thanThe third algorithm, NoX, is a fully stochastic specialization of RHS for codes with a variable node degree 2 that offers similar performance, but at a significantly lower computational complexity. less thanbrgreater than less thanbrgreater thanWe study the performance and complexity of the algorithms; noting that all have lower per-iteration complexity than SPA and that RHS can have comparable average per-codeword computational complexity, and NoX a lower one.

The appearance of radix-2(2) was a milestone in the design of pipelined FFT hardware architectures. Later, radix-2(2) was extended to radix-2(k). However, radix-2(k) was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2(k) feedforward (MDC) FFT architectures. In feedforward architectures radix-2(k) canbe used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which makes them suitable for the most demanding applications. Indeed, the proposed radix-2(k) feedforward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix-2(k) feedforward architectures not only offer an attractive solution for current applications, but also open up a new research line on feedforward structures.

This paper deals with time-varying finite-length impulse response (FIR) filters used for reconstruction of two-periodic nonuniformly sampled signals. The complexity of such reconstructorsincreases as their bandwidth approaches the whole Nyquist band. Reconstructor design that yields minimum reconstructor order requires expensive online redesign while those methods that simplify online redesign result in higher reconstructor complexity. This paper utilizes a two-rate approach to derive a single-rate structure where part of the complexity of the reconstructor is moved to a symmetric filter so as to reduce the number of multipliers. The symmetric filter is designed such that it can be used for all time-skew errors within a certain range, thereby reducing the number of coefficients that need online redesign. The basic two-rate based reconstructor is further extended to completely remove the need for online redesign at the cost of a slight increase in the total number of multipliers.

This paper introduces multimode transmultiplexers (TMUXs) in which the Farrow structure realizes the polyphase components of general lowpass interpolation/decimation filters. As various lowpass filters are obtained by one set of common Farrow subfilters, only one offline filter design enables us to cover different integer sampling rate conversion (SRC) ratios. A model of general rational SRC is also constructed where the same fixed subfilters perform rational SRC. These two SRC schemes are then used to construct multimode TMUXs. Efficient implementation structures are introduced and different filter design techniques such as minimax and least-squares (LS) are discussed. By means of simulation results, it is shown that the performance of the transmultiplexer (TMUX) depends on the ripples of the filters. With the error vector magnitude (EVM) as the performance metric, the LS method has a superiority over the minimax approach.

The coefficient decimation technique for reconfigurable FIR filters was recently proposed as a filter structure with low computational complexity. In this brief, we propose to design these filters using linear programming taking all configuration modes into account, instead of only considering the initial reconfiguration mode as in previous works. Minimax solutions with significantly lower approximation errors compared to the straightforward design method in earlier works are obtained. In addition, some new insights that are useful when designing coefficient decimation filters are provided.

This correspondence introduces a technique for efficient realization of wide-band finite-length impulse response (FIR) linear and timeinvariant (LTI) systems. It divides the overall frequency region into three subregions through lowpass, bandpass, and highpass filters realized in terms of only one filter. The actual function to be approximated is in the low- and high-frequency regions realized using periodic subsystems. In this way, one can realize an overall wide-band LTI function in terms of three low-cost subblocks, leading to a reduced overall arithmetic complexity as compared to the regular realization. A systematic design technique is provided and a detailed example shows multiplication and addition savings of 62 and 48 percent, respectively, for a fractional-order differentiator with a 96 percent utilization of the bandwidth. Another example shows that the savings increase/decrease with increased/decreased bandwidth.

In this work we consider optimized twiddle factor multipliers based on shift-and-add-multiplication. We propose a low-complexity structure for twiddle factors with a resolution of 32 points. Furthermore, we propose a slightly modified version of a previously reported multiplier for a resolution of 16 points with lower round-off noise. For completeness we also include results on optimal coefficients for eight-points resolution. We perform finite word length analysis for both coefficients and round-off errors and derive optimized coefficients with minimum complexity for varying requirements.

This brief presents novel circuits for calculating bit reversal on a series of data. The circuits are simple and consist of buffers and multiplexers connected in series. The circuits are optimum in two senses: they use the minimum number of registers that are necessary for calculating the bit reversal and have minimum latency. This makes them very suitable for calculating the bit reversal of the output frequencies in hardware fast Fourier transform (FFT) architectures. This brief also proposes optimum solutions for reordering the output frequencies of the FFT when different common radices are used, including radix-2, radix-2(k), radix-4, and radix-8.

This paper presents a digital background calibration technique that measures and cancels offset, linear and nonlinear errors in each stage of a pipelined analog to digital converter (ADC) using a single algorithm. A simple two-step subranging ADC architecture is used as an extra ADC in order to extract the data points of the stage-under-calibration and perform correction process without imposing any changes on the main ADC architecture which is the main trend of the current work. Contrary to the conventional calibration methods that use high resolution reference ADCs, averaging and chopping concepts are used in this work to allow the resolution of the extra ADC to be lower than that of the main ADC.

This paper introduces a class of wide-band linear-phase finite-length impulse response (FIR) differentiators. It is based on two-rate and frequency-response masking techniques. It is shown how to use these techniques to obtain all four types of linear-phase FIR differentiators. Design examples demonstrate that differentiators in this class can achieve substantial savings in arithmetic complexity in comparison with conventional direct-form linear-phase FIR differentiators. The savings achievable depend on the bandwidth and increase with increasing bandwidth beyond the break-even points which are in the neighborhood of 90% (80%) of the whole bandwidth for Type II and III (Type I and IV) differentiators. The price to pay for the savings is a moderate increase in the delay and number of delay elements. Further, in terms of structural arithmetic operations, the proposed filters are comparable to filters based on piecewise-polynomial impulse responses. The advantage of the proposed filters is that they can be implemented using non-recursive structures as opposed to the polynomial-based filters which are implemented with recursive structures.

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The generation of a canonical signed digit representation from a binary representation is revisited. Based on the property that each nonzero digit is surrounded by a zero digit, a hardware-efficient conversion method using bypass instead of carry propagation is proposed. The proposed method requires less area per digit and the required bypass signal can be generated or propagated with only a single NOR gate. It is shown that the proposed converter outperforms previous converters and a look-ahead circuitry to speed up the generation of bypass signals is also proposed.

This paper discusses two approaches for the baseband processing part of cognitive radios. These approaches can be used depending on the availability of (i) a composite signal comprising several user signals or, (ii) the individual user signals. The aim is to introduce solutions which can support different bandwidths and center frequencies for a large set of users and at the cost of simple modifications on the same hardware platform. Such structures have previously been used for satellite-based communication systems and the paper aims to outline their possible applications in the context of cognitive radios. For this purpose, dynamic frequencyband allocation (DFBA) and reallocation (DFBR) structures based on multirate building blocks are introduced and their reconfigurability issues with respect to the required reconfigurability measures in cognitive radios are discussed.

We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous D registers. A chip was fabricated in a standard 130-nm CMOS technology holding two versions of a pipelined 16-bit adder. First version employed the proposed method, and second version used conventional static CMOS logic circuits and TSPC registers. The respective device counts are 1190 and 684, and maximal operating frequencies 450 and 375 MHz. Frequency domain measurements were performed at the substrate node with on-chip generated sinusoidal and pseudo-random data at a clock frequency of 300 MHz. The sinusoidal case resulted in the largest frequency components, where an 8.5 dB/Hz decrease in maximal power is measured for the proposed circuitry at a cost of three times larger power consumption.

This paper introduces two classes of cosine-modulated causal and stable filter banks (FBs) with near perfect reconstruction (NPR) and low implementation complexity. Both classes have the same infinite-length impulse response (IIR) analysis FB but different synthesis FBs utilizing IIR and finite-length impulse response (FIR) filters, respectively. The two classes are preferable for different types of specifications. The IIR/FIR FBs are preferred if small phase errors relative to the magnitude error are desired, and vice versa. The paper provides systematic design procedures so that PR can be approximated as closely as desired. It is demonstrated through several examples that the proposed FB classes, depending on the specification, can have a lower implementation complexity compared to existing FIR and IIR cosine-modulated FBs (CMFBs). The price to pay for the reduced complexity is generally an increased delay. Furthermore, two additional attractive features of the proposed FBs are that they are asymmetric in the sense that one of the analysis and synthesis banks has a lower computational complexity compared to the other, which can be beneficial in some applications, and that the number of distinct coefficients is small, which facilitates the design of FBs with large numbers of channels.

Multiplication by constants can be efficiently realized using shifts, additions, and subtractions. In this work we consider how to select a fixed-point value for a real valued, rational, or floating-point coefficient to obtain a low-complexity realization. It is shown that the process, denoted addition aware quantization, often can determine coefficients that has as low complexity as the rounded value, but with a smaller approximation error by searching among coefficients with a longer wordlength.

This paper introduces a structure for the compensation of frequency-response mismatch errors in M-channel time-interleaved analog-to-digital converters (ADCs). It makes use of a number of fixed digital filters, approximating differentiators of different orders, and a few variable multipliers that correspond to parameters in polynomial models of the channel frequency responses. Whenever the channel frequency responses change, which occurs from time to time in a practical time-interleaved ADC, it suffices to alter the values of these variable multipliers. In this way, expensive on-line filter design is avoided. The paper includes several design examples that illustrate the properties and capabilities of the proposed structure.

In this paper, we present a novel complex discrete-time filter. This is a fractionally delaying (FD) Hilbert transform filter (HTF) further called the FD HTF. The filter is based on a pair of rotated variable fractional delay (VFD) filters. It is capable of performing the Hilbertian as well as VFD filtering of the incoming discrete-time signal at the same time. Thus, one can substitute a cascade of the HTF and the VFD filters with an aggregated filter proposed here. The technique is simple to implement. The advantages lie in lower total delay introduced by the compound filter and in a modular structure. The rotated VFD filters in the pair differ only in the value of one parameter-the VFD. The proposed FD HTF can be applied to adaptive quadrature sub-sample estimation of delay. © 2008 IEEE.

This paper introduces a multimode transmultiplexer (TMUX) structure capable of generating a large set of user-bandwidths and center frequencies. The structure utilizes fixed integer sampling rate conversion (SRC) blocks, Farrow-based variable interpolation and decimation structures, and variable frequency shifters. A main advantage of this TMUX is that it needs only one filter design beforehand. Specifically, the filters in the fixed integer SRC blocks as well as the subfilters of the Farrow structure are designed only once. Then, all possible combinations of bandwidths and center frequencies are obtained by properly adjusting the variable delay parameter of the Farrow-based filters and the variable parameters of the frequency shifters. The paper includes examples for demonstration. It also shows that, using the rational SRC equivalent of the Farrow-based filters, the TMUX can be described in terms of conventional multirate building blocks which may be useful in further analysis of the overall system.

This paper proposes polynomial impulse response finite-impulse response filters for reconstruction of two-periodic nonuniformly sampled signals. The foremost advantages of using these reconstruction filters are that on-line filter design thereby is avoided and subfilters with fixed dedicated multipliers can be employed in an implementation. The overall implementation cost can in this way be reduced substantially in applications where the sampling pattern changes from time to time. The paper presents two different design techniques that yield optimum filters in the least-squares and minimax senses, respectively. Design examples are included that illustrate the benefits of the proposed filters. © 2007 IEEE.

This paper offers two main contributions to the theory of low-delay frequency-response masking (FRM) finite impulse response (FIR) filters. First, a thorough investigation of the low-delay FRM FIR filters and their subfilters or three different structures, referred to as narrow-, wide-, and middle-band filter structures, is given. The investigation includes discussions on delay distribution over the subfilters as well as estimation of the optimal periodicity of the periodic model filter. Second, systematic design procedures are given, with explicit formulas for distribution of the ripples and the delay to the subfilters. For each of the three structures, two design procedures are given that include joint optimization of the subfilters. The first proposal uses partly linear-phase FIR subfilters and partly low-delay FIR subfilters. Thus, it has a lower arithmetic complexity compared to the second proposal, which has exclusively low-delay FIR subfilters. The second proposal is instead more flexible and can handle a broader range of specifications. The design procedures result in low-delay FIR filters with a lower arithmetic complexity compared to previous results, for specifications with low delay and narrow transition band. © Birkhauser Boston 2007.

A crucial issue in the next-generation satellite-based communication systems is the satellite on-board reallocation of information which requires digital flexible frequency-band reallocation (FBR) networks. This paper introduces a new class of flexible FBR networks based on variable oversampled complex-modulated filter banks (FBs). The new class can outperform the previously existing ones when all the aspects flexibility, low complexity and inherent parallelism, near-perfect frequency-band reallocation, and simplicity are considered simultaneously.

Multiple constant multiplication (MCM) is an efficient way of implementing several constant multiplications with the same input data. The coefficients are expressed using shifts, adders, and subtracters. By utilizing redundancy between the coefficients the number of adders and subtracters is reduced resulting in a low complexity implementation. However, for digit-serial arithmetic a shift requires a flip-flop, and, hence, the number of shifts should be taken into consideration as well. In this work we investigate the area, speed, power trade-offs for implementation of FIR filters using MCM and digit-serial arithmetic. We also introduce an algorithm for reducing both the number of adders and subtracters as well as the number of shifts.

Data representations for LDPC decoders using the sum-product algorithm in the log-likelihood domain are considered. It is suggested that the look-up table implementation of the domain transform function is separated into two parts, allowing a compact representation of the internal state data. Memories and bus widths can be reduced by typically 16\%, while the imposed hardware overhead is insignificant.

An asynchronous wrapper with novel handshake circuits for data communication in globally asynchronous locally synchronous (GALS) systems is proposed. The handshake circuits include two communication ports and a local clock generator. Two approaches for the implementation of communication ports are presented, one with pure standard cells and the others with Muller-C elements. The detailed design methodology for GALS systems is given and the circuits are validated with VHDL and circuits simulation in standard CMOS technology

This paper introduces novel linear-phase finite-impulse response (FIR) interpolation, decimation, and Mth-band filters utilizing the Farrow structure. In these new overall filters, each polyphase component (except for one term) is realized using the Farrow structure with a distinct fractional delay. The corresponding interpolation/decimation structures can therefore be implemented using only one set of linear-phase FIR subfilters and one set of multipliers that correspond to the distinct fractional delays. The main advantage of the proposed structures is that they are flexible as to the conversion factors, and this also for an arbitrary set of integer factors, including prime numbers. In particular, they can simultaneously implement several converters at a low cost. The proposed filters can be used to generate both general filters and Mth-band filters for interpolation and decimation by the integer factor M. (In this paper, a general filter for interpolation and decimation by M means a filter having a bandwidth of approximately p/M without the restriction that p/M be included in the transition band. This is in contrast to ah Mth-band filter whose transition band does include p/M.) In both cases, the overall filter design problem can be posed as a convex problem, the solution of which is globally optimum. Design examples are included in the paper illustrating the properties and potentials of the proposed filters. © 2005 IEEE.

The problem of selecting codewords for memoryless low-power bus coding is considered. A graph-based procedure is proposed to obtain a subset of all possible codewords with minimum average energy consumption. The procedure can be applied to arbitrary cost models.

This paper introduces new multirate infinite-length impulse-response (IIR) filter structures for arbitrary bandwidths. The overall filters have the same input and output sample rates. Multirate techniques are only used internally in order to improve the efficiency. The overall filters make use of an IIR filter for the actual filtering,. periodic allpass filters for constructing complementary filters, and linear-phase finite-length impulse-response (FIR) filters for the sampling rate alterations. There are the following two main reasons for introducing the new filters: 1) they can be used to obtain so called high-speed IIR filters (i.e., filters able to operate at a high sample rate) with lower complexity than that achievable with single-rate high-speed filters and 2) they can be used to obtain approximately linear-phase filters with substantially lower complexity than that achievable with single-rate filters. The overall filters are designed by separately optimizing a number of linear-phase (possibly half-band) FIR filters, and one IIR filter being realizable as a parallel connection of two allpass filters. Design examples are included illustrating the usefulness of the proposed filters.

This paper introduces new tree-structured uniform-band and octave-band digital filter banks (FBs). These FBs make use of half-band IIR filters in the analysis FBs and FIR filters in the synthesis FBs. The resulting FBs are asymmetric in the sense that the analysis FB has a very low arithmetic complexity whereas that in the synthesis FB is higher. However, compared with other asymmetric FBs, the proposed ones have in many cases a lower overall arithmetic complexity and delay. The proposed FBs have magnitude distortion but no phase distortion, further, the aliasing components are either zero (uniform-band case) or approximately zero (octave-band case). The FBs are designed using linear and nonlinear programming. Design examples are included demonstrating the properties of the proposed filters banks. ⌐ 2003 Published by Elsevier B.V.

Multirate filter banks make use of analysis and synthesis filter banks. This paper introduces two-channel digital and hybrid analog/digital multirate filter banks where either the analysis or synthesis filters have a very low complexity. Such filter banks find application, for example, in high-speed analog-to digital converters where it is essential to minimize the complexity of the discrete-time or analog filters. The proposed digital filter banks are approximately perfect reconstruction (PR) filter banks, whereas the hybrid analog/digital filter banks can be chosen to be either approximately PR or approximately perfect magnitude reconstruction filter banks. The design is performed by first optimizing the digital or analog analysis filters and then, with the analysis filters fixed, optimizing the digital synthesis filters. This design procedure makes it possible to obtain analysis filters of very low order and complexity. The overall complexity is also low. Further, the proposed filter banks are, in all cases, very easy to design by making use of well-known and reliable optimization techniques, in particular, as small distortion and aliasing as desired are readily obtained because they are controlled in a linear programming problem. Several design examples are included, illustrating the properties of the proposed filter banks.

In this work, a new algorithm called nonrecursive signed common subexpression elimination (NR-SCSE) is discussed, and several Applications in the area of multiplierless finite-impulse response (FIR) filters are developed. While the recursive utilization of a common subexpression generates a high logic depth into the digital structure, the NR-SCSE algorithm allows the designer to overcome this problem by using each subexpression once. The paper presents a complete description of the algorithm, and a comparison with two other well-known options: the graph synthesis, and the classical common subexpression elimination technique. Main results show that the NR-SCSE implementations of several benchmark circuits offer the best relation between occupied area and logic depth respect to the previous values published in the technical literature.

In this work we discuss the realization of constant multiplication using a minimum number of carry-save adders. We consider both non-redundant and carry-save representation for the input data. For both cases we present all possible interconnection topologies, using up to six and five adders, respectively. These are sufficient to realize constant multiplications for all coefficients with a wordlength up to 19 bits.

In this work modelling of the power consumption for ripple-carry adders implemented in CMOS is considered. Based on the switching activity of each input bit, two switching models, one full and one simplified, are derived. These switching models can be used to derive the average energy consumed for one computation. This work extends previous results by introducing a data dependent power model, i.e., correlated input data is considered. Examples show that the switching model is accurate, while there are some differences in the power consumption. This is due to the fact that not all switching in the ripple-carry adder is rail-to-rail (full swing) in the actual implementation.

Subspace identification is a classical and very well studied problem in system identification. The problem was recently posed as a convex optimization problem via the nuclear norm relaxation. Inspired by robust PCA, we extend this framework to handle outliers. The proposed framework takes the form of a convex optimization problem with an objective that trades off fit, rank and sparsity. As in robust PCA, it can be problematic to find a suitable regularization parameter. We show how the space in which a suitable parameter should be sought can be limited to a bounded open set of the two-dimensional parameter space. In practice, this is very useful since it restricts the parameter space that is needed to be surveyed.

An oversampled digital-to-analog converter including digital Sigma Delta modulator and semi-digital FIR filter can be employed in the transmitter of the VDSL2 technology. To select the optimum set of coefficients for the semi-digital FIR filter, an integer optimization problem is formulated in this work, where the model includes the FIR filter magnitude metrics as well as Sigma Delta modulator noise transfer function. The semi-digital FIR filter is optimized with respect to magnitude constraints according to the International Telecommunication Union Power Spectral Density mask for VDSL2 technology and minimizing analog cost as the objective function. Utilizing the semi-digital FIR filter with one bit DACs, high linearity required in high-bandwidth profiles of VDSL2, can be achieved. The resolution of the conventional DACs are limited by the mismatch between DAC unit elements. By utilizing one-bit DACs in semi-digital FIR filter, there will be less degradation caused by mismatch between unit elements. The optimization problem is solved in two conditions; fixed passband gain and variable passband gain. It is shown in this paper that 38% saving in total number of unit elements can be achieved by employing variable passband gain in the optimization problem.

In this paper, we explore two nonrecursive reconstructors which recover the uniform-grid samples from the output of a time-interleaved analog-to-digital converter (TI-ADC) that uses some of the sampling instants for estimating the mismatches in the TI-ADC. Nonuniform sampling occurs due to timing mismatches between the individual channel ADCs and also due to missing input samples. Compared to a previous solution, the reconstructors presented here offer substantially lower computational complexity.

This paper presents new radix-2 and radix-22 constant geometry fast Fourier transform (FFT) algorithms for graphics processing units (GPUs). The algorithms combine the use of constant geometry with special scheduling of operations and distribution among the cores. Performance tests on current GPUs show a significant improvements compared to the most recent version of NVIDIA’s well-known CUFFT, achieving speedups of up to 5.6x.

This paper introduces a finite-length impulse response (FIR) digital filter having both a variable fractional delay (VFD) and a variable phase shift (VPS). The realization is reconfigurable online without redesign and without transients. It can be viewed as a generalization of the VFD Farrow structure that offers a VPS in addition to the regular VFD. The overall filter is composed of a number of fixed subfilters and a few variable multipliers whose values are determined by the desired FD and PS values. It is designed offline in an iterative manner, utilizing reweighted l(1)-norm minimization. This design procedure generates fixed subfilters with many zero-valued coefficients, typically located in the impulse response tails.

Nonuniform sampling occurs in time-interleaved analog-to-digital converters (TI-ADC) due to timing mismatches between the individual channel analog-to-digital converters (ADCs). Such nonuniformly sampled output will degrade the achievable resolution in a TI-ADC. To restore the degraded performance, digital time-varying reconstructors can be used at the output of the TI-ADC, which in principle, converts the nonuniformly sampled output sequence to a uniformly sampled output. As the bandwidth of these reconstructors increases, their complexity also increases rapidly. Also, since the timing errors change occasionally, it is important to have a reconstructor architecture that requires fewer coefficient updates when the value of the timing error changes. Multivariate polynomial impulse response reconstructor is an attractive option for an M-channel reconstructor. If the channel timing error varies within a certain limit, these reconstructors do not need any online redesign of their impulse response coefficients. This paper proposes a technique that can be applied to multivariate polynomial impulse response reconstructors in order to further reduce the number of fixed-coefficient multipliers, and thereby reduce the implementation complexity.

In this work, we present an analytical study of aliasing image spurs problem in digital-RF modulators. The inherent finite image rejection ratio of this types modulators is conceptually discussed. A pulse amplitude modulation (PAM) model of the converter is used in the theoretical discussion. Behavioral level simulation of the digital-RF converter model is included. Finite image rejection is a limiting issue in this architecture, and Digital-IF mixing is used to alleviate the problem which is also reviewed and simulated.

This paper introduces a new class of linear-phase Nyquist (Mth-band) FIR interpolators and decimators based on tree structures. Through design examples, it is shown that the proposed converter structures have a substantially lower computational complexity than the conventional single-stage converter structures. The complexity is comparable to that of multi-stage Nyquist converters, although the proposed ones tend to have a somewhat higher complexity. A main advantage of the proposed structures is however that they can be used for arbitrary integer conversion factors, thus including prime numbers which cannot be handled by the regular multi-stage Nyquist converters.

This paper introduces a realization of finite-length impulse response (FIR) filters with simultaneously variable bandwidth and fractional delay (FD). The realization makes use of impulse responses which are two-dimensional polynomials in the bandwidth and FD parameters. Unlike previous polynomial-based realizations, it utilizes the fact that a variable FD filter is typically much less complex than a variable-bandwidth filter. By separating the corresponding subfilters in the overall realization, significant savings are thereby achieved. A design example, included in the paper, shows about 65 percent multiplication and addition savings compared to the previous polynomial-based realizations. Moreover, compared to a recently introduced alternative fast filter bank approach, the proposed method offers significantly smaller group delays and group delay errors.

Time-interleaved analog-to-digital converters (ADCs) exhibit offset, gain, and time-skew errors due to channel mismatches. The time skews give rise to a nonuniformly sampled signal instead of the desired uniformly sampled signal. This introduces the need for a digital signal reconstructor that takes the "nonuniform samples" and generates the "uniform samples". In the general case, the time skews are frequency dependent, in which case a generalization of nonuniform sampling applies. When the bandwidth of a digital reconstructor approaches the whole Nyquist band, the computational complexity may become prohibitive. This paper introduces a new scheme with reduced complexity. The idea stems from recent multirate-based efficient realizations of linear and time-invariant systems. However, a time-interleaved ADC (without correction) is a time-varying system which means that these multirate-based techniques cannot be used straightforwardly but need to be appropriately analyzed and extended for this context.

This paper proposes a method to design low-delay fractional delay (FD) filters, using the Farrow structure. The proposed method employs both linear-phase and nonlinear-phase finite-length impulse response (FIR) subfilters. This is in contrast to conventional methods that utilize only nonlinear-phase FIR subfilters. Two design cases are considered. The first case uses nonlinear-phase FIR filters in all branches of the Farrow structure. The second case uses linear-phase FIR filters in every second branch. These branches have milder restrictions on the approximation error. Therefore, even with a reduced order, for these linear-phase FIR filters, the approximation error is not affected. However, the arithmetic complexity, in terms of the number of distinct multiplications, is reduced by an average of 30%. Design examples illustrate the method.

Rotations by angles that are fractions of the unit circle find applications in e.g. fast Fourier transform (FFT) architectures. In this work we propose a new rotator that consists of a series of stages. Each stage calculates a micro-rotation by an angle corresponding to a power-of-three fractional parts. Using a continuous powers-of-three range, it is possible to carry out all rotations required. In addition, the proposed rotators are compared to previous approaches, based of shift-and-add algorithms, showing improvements in accuracy and number of adders.

This paper presents an analog receiver front-end design (AFE) for capacitive body-coupled digital baseband receiver. The most important theoretical aspects of human body electrical model in the perspective of capacitive body-coupled communication (BCC) have also been discussed and the constraints imposed by gain and input-referred noise on the receiver front-end are derived from digital communication theory. Three different AFE topologies have been designed in ST 40-nm CMOS technology node which is selected to enable easy integration in today's system-on-chip environments. Simulation results show that the best AFE topology consisting of a multi-stage AC-coupled preamplifier followed by a Schmitt trigger achieves 57.6 dB gain with an input referred noise PSD of 4.4 nV/√Hz at 6.8 mW.

An analysis of frequency control techniques for inverter based ring oscillators is presented. The aim of this study is to aid the circuit designer in architecture selection appropriate for a specific application. A brief discussion on ring oscillators is presented followed by an overview of the various control schemes. The circuits are realized in a 40 nm CMOS technology and simulated using Spectre. Based on simulation results the different control schemes are characterized in terms power consumption, tuning range and noise performance so as to guide the designer about the control scheme selection.

In this paper, modified, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and power consumption. Two different architectures are investigated, both have variable configurations of the input and output word-length (i.e., the physical resolution of the DAC). A modified architecture, termed in this work as a composite architecture (CA), shows about 9 dB increase in SNR while maintaining a power-consumption at the same level as that of a so-called hybrid architecture (HA). The power estimation is done for modulators on the RTL level using a standard cell library in a 65-nm technology. The modulators are operated at a sampling frequency of 2 GHz.

Pipelined analog-to-digital converters (ADCs) achieve low to moderate resolutions at high bandwidths while sigma-delta (ΣΔ) ADCs provide high resolution at moderate bandwidths. A switched-capacitor (SC) block which can function as an integrator or an MDAC can be used to implement a reconfigurable ADC (R-ADC) which supports both these types of architectures. Through the use of high level models this work attempts to derive the capacitance and critical opamp parameters such as DC gain and bandwidth of the SC blocks in a reconfigurable ADC. Scaling of capacitance afforded by the noise shaping property of ΣΔ loops as well as the inter-stage gain of pipelined ADCs is used to minimize the total capacitance. This work can be used as reference material to understand some of the design trade-offs in R-ADCs.sigma-delta ADCs

In this work a systematic method to generate all possible fast Fourier transform (FFT) algorithms is proposed based on the relation to binary trees. The binary tree is used to represent the decomposition of a discrete Fourier transform (DFT) into sub-DFTs. The radix is adaptively changed according to compute sub-DFTs in proposed decomposition. In this work we determine the number of possible algorithms for 2ⁿ-point FFTs with radix-2 butterfly operation and propose a simple method to determine the twiddle factor indices for each algorithm based on the binary tree representation.

Matrix inversion is sensitive towards the number representation used. In this paper simulations of matrix inversion with numbers represented in the fixed-point and logarithmic number systems (LNS) are presented. A software framework has been implemented to allow extensive simulation of finite wordlength matrix inversion. Six different algorithms have been used and results on matrix condition number, wordlength, and to some extent matrix size are presented. The simulations among other things show that the wordlength requirements differ significantly between different algorithms in both fixed-point and LNS representations. The results can be used as a starting point for a matrix inversion hardware implementation.

Matrix inversion is a key operation in for instance adaptivefilters and MIMO communication system receivers. For ill-conditionedchannel matrices long wordlengths are required for fixed-point implementationof matrix inversion. In this work, the wordlength/error tradeoffsfor matrix inversion using different algorithms with fixed-point andlogarithmic number systems (LNS) are considered. LNS provides higherresolution for small numbers and a larger dynamic range. Also, it willalter the cost of the basic operations in the algorithms. The results showthat also the wordlength required to achieve a comparable error differsignificantly between different algorithms and for most algorithms isreduced for LNS compared to fixed-point.

The use of rate-compatible error correcting codes offers severaladvantages as compared to the use of fixed-rate codes: a smooth adaptationto the channel conditions, the possibility of incremental Hybrid ARQschemes, as well as simplified code representations in the encoder anddecoder. In this paper, the implementation of a decoder for rate-compatiblequasi-cyclic LDPC codes is considered. The decoder uses check node mergingto increase the convergence speed of the algorithm. Check node mergingallows the decoder to achieve the same performance with a significantlylower number of iterations, thereby increasing the throughput.

The feasibility of a check node merging decoder is investigated for codesfrom IEEE 802.16e and IEEE 802.11n. The faster convergence rate of the checknode merging algorithm allows the decoder to be implemented using lowerparallelization factors, thereby reducing the logic complexity. The designshave been synthesized to an Altera Cyclone II FPGA, and results showsignificant increases in throughput at high SNR.

In this work, a design method for narrow-band and wide-band frequency-response masking FIR filters is proposed. As opposed to most previous works, the design method is not based on a periodic model filter. Instead, the masking filter is designed for a given stopband edge. The model filter design is based on optimizing the sparseness of the filter, and, hence, the resulting model filter is not required to be periodic.

In this work, we investigate the problem of computing any requested set of power terms in parallel using summations trees. This problem occurs in applications like polynomial approximation, Farrow filters (polynomial evaluation part) etc. In the proposed technique, the partial product of each power term is initially computed independently. A redundancy check is then made in each and among all partial products matrices at bit level. The redundancy here relates to the fact that same three partial products may be present in more than one columns, and, hence, can be mapped to the same full adder. The proposed algorithm is tested for different sets of powers and wordlengths to exploit the sharing potential.

The power modeling of different realizations of cascaded integrator-comb (CIC) decimation filters has been a subject of several recent works. In this work we have extended these with modeling of leakage power, which is an important factor since the input sample rate may differ several orders of magnitude. Furthermore, we have pointed out the importance of the input wordlength on the comparison of recursive and nonrecursive implementations.

A less complex and generic channel estimation algorithm for long term evolution (LTE) and digital video broadcasting-handheld (DVB-H) downlink standards, is proposed. The technique, here referred to as minimum mean square error sliding window (MSW) technique, obtains less computational complexity than previous mean squared error (MSE) algorithms [3] at the cost of some 0.3 dB less SNR. The computational complexity is decreased by a factor 3 for the LTE 5-MHz downlink case and by 30 for the DVB-H standard case. Simulated results in terms of mean squared error and bit error rates are presented for a quadrature phase-shift keying (QPSK) systems with interleaving and coding of the data. All simulations are done at the behaviolar-level level.

In this paper a calibration technique for high-resolution, flash analog- to-digital converters (ADCs) based on histogram test methods is proposed. A probability density function, PDF, generator circuit is utilized to generate a triangular signal with a constant PDF, i.e., uniform distribution, as a test signal. In the proposed technique both offset estimation and trimming are performed without imposing any changes on the comparator structure in the ADC. The proposed algorithm estimates the offset values and stores them in a RAM. The trimming circuit uses the stored values and performs the trimming by adjusting the reference voltages to the comparators. An 8-bit flash ADC with a 1-V reference voltage, a comparator offset distribution with σ_os ≈ 30 mV, and a 10-bit test signal with about 3% nonlinearity are used in the simulations. The results show that the calibration improves the DNL and INL from about 3.6/3.9 LSB to about 0.9/0.75 LSB, respectively.

This work discusses a link between two previously reported ideas in high-speed digital-to-analog converter (DAC) design: linear approximation with analog interpolation techniques and an RF DAC concept where oscillatory pulses are used to combine a DAC with an up-conversion mixer. An architecture is proposed where we utilize analog interpolation techniques, but using sinusoidal rather than linear interpolation in order to allocate more energy to higher Nyquist ranges as is commonly done in RF DACs. The interpolation is done in the time domain, such that it approximates the oscillating signal from the RF DAC concept to modulate the signal up to a higher Nyquist range. Then, instead of taking the output from within the Nyquist range, as in conventional case, the output of the DAC is taken from higher images. The proposed architecture looks promising for future implementations in high-speed DACs as it can be used in RF DAC or modified versions of digital-to-RF converters (DRFCs). Simulation results and theoretical descriptions are presented to support the idea.

This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process. The “pseudo” switched-capacitor (SC) PGA architecture buffers the video signal, without switching, during the active video. The SC circuitry is used for setup of DC operating point during horizontal and vertical blanking periods. Additionally, it compensates for the `sync-tip' of analog video signals to an equal blanking level for increased dynamic range to the digitizer following the PGA. The operational transconductance amplifier (OTA) employed as main amplifier in the PGA is a pseudo-differential, positive-feedback input stage architecture with a common-mode feedforward (CMFF) technique. The common-mode feedback (CMFB) is provided once two OTAs are cascaded. Schematic-level simulation results show that the OTA maintains a -3-dB bandwidth of 550 MHz, while keeping the distortion HD₃ at -60 dB for a 30-MHz, 850 mV_pp high definition video signal. The 88 dB DC gain is distributed among four OTA stages and the overall, combined PGA achieves a signal-to-noise ratio of 63 dB. Due to only two stacked transistors, it achieves high output swing of ±0.85 V, 1240 V/μs slew rate while consuming 10.4 mW power.

In this paper, we propose higher point FFT (fast Fourier transform) algorithms for a single delay feedback pipelined FFT architecture considering the 4096-point FFT. These algorithms are different from each other in terms of twiddle factor multiplication. Twiddle factor multiplication complexity comparison is presented when implemented on Field-Programmable Gate Arrays (FPGAs) for all proposed algorithms. We also discuss the design criteria of the twiddle factor multiplication. Finally it is shown that there is a trade-off between twiddle factor memory complexity and switching activity in the introduced algorithms.

In this paper, we propose equivalent radix-2² algorithms and evaluate them based on twiddle factor switching activity for a single delay feedback pipelined FFT architecture. These equivalent pipeline FFT algorithms have the same number of complex multipliers with the same resolution as the radix-2². It is shown that the twiddle factor switching activity of the equivalent algorithms is reduced with up to 40% for some of the equivalent algorithms derived for N = 256.

This paper introduces reconfigurable nonuniform transmultiplexers (TMUXs) based on uniform modulated filter banks (FBs). Polyphase components, of any user, are processed by a number of synthesis FB and analysis FB branches of a uniform TMUX. One branch, of the TMUX, represents one granularity band and any user occupies integer multiples of a granularity band. By adjusting the number of branches, assigned to each user, a nonuniform TMUX is obtained. This only requires adjustable commutators which add no extra arithmetic complexity. The application of both cosine modulated and modified discrete Fourier transform FBs are considered and the formulations related to the appropriate choice of parameters are outlined. Examples are provided for illustration.

An optimization algorithm for the design of puncturing patterns for low-density parity-check codes is proposed. The algorithm is applied to the base matrix of a quasi-cyclic code, and is expanded for each block size used. Thus, storing puncturing patterns specific to each block size is not required. Using the optimization algorithm, the number of 1-step recoverable nodes in the base matrix is maximized. The obtained sequence is then used as a base to obtain longer puncturing sequences by a sequential increase of the allowed recovery delay. The proposed algorithm is compared to one previous greedy algorithm, and shows superior performance for high rates when the heuristics are applied to the base matrix in order to create block size-independent puncturing patterns.

In this work we consider high-speed FIR filter architectures implemented using, possibly pipelined, carry-save adder trees for accumulating the partial products. In particular we focus on the mapping between partial products and full adders and propose a technique to reduce the number of carry-save adders based on the inherent redundancy of the partial products. The redundancy reduction is performed on the bit-level to also work for short wordlength data such as those obtained from sigma-delta modulators.

Sub-expression sharing is a technique that can be applied to reduce the complexity of linear time-invariant non-recursive computations by identifying common patterns. It has recently been proposed that it is possible to improve the performance of single and multiple constant multiplication by identifying overlapping digit patterns. In this work we extend the concept of overlapping digit patterns to arbitrary shift dimensions, such as shift in time (FIR filters). © 2010 IEEE.

We present a method for controlling a dynamical system using real-time fMRI. The objective for the subject in the MR scanner is to balance an inverse pendulum by activating the left or right hand or resting. The brain activity is classified each second by a neural network and the classification is sent to a pendulum simulator to change the force applied to the pendulum. The state of the inverse pendulum is shown to the subject in a pair of VR goggles. The subject was able to balance the inverse pendulum both with real activity and imagined activity. The developments here have a potential to aid people with communication disabilities e.g., locked in people. It might also be a tool for stroke patients to be ableto train the damaged brain area and get real-time feedback of when they do it right.

In this work we consider scaling of fractional delay filters using the Farrow structure. Based on the observation that the subfilters approximate the Taylor expansion of a differentiator, we derive estimates of the L₂-norm scaling values at the outputs of each subfilter as well as at the inputs of each delay multiplier. The scaling values can then be used to derive suitable wordlengths in a fixed-point implementation.

In this work we consider structures for simultaneous multiplication by a small set of two pairwise coefficients where the coefficients are the real and imaginary part of a limited number of points uniformly spread on the unit circle. Hence, each such multiplier forms half of a complex multiplier suitable for twiddle factor multiplication in FFT architectures. Based on trigonometric identities we propose a multiplier for a unit circle resolution of 32 points. Also, we revisit an earlier proposed multiplier for 16 points and show that the complexity can be reduced by using minimum adder constant multipliers compared with the earlier proposed CSD-based multipliers.

This paper discusses some issues related to the filter design in a class of multimode transmultiplexers (TMUXs). These TMUXs cover a large set of frequency division multiplexed (FDM) scenarios with simple reconfigurations. The reconfiguration is performed by changing the values of some multipliers. The paper outlines a direct filter design to decrease the level of inter-symbol and inter-carrier interference by the use of time-varying periodic filters. These time-varying periodic filters are derived from the known FDM scenarios and they are included as additional constraints in the filter design. Both minimax and constrained least-squares approaches are treated and it is shown that by including the additional constraints, the level of the TMUX noise can be reduced. This results in a better approximation of perfect reconstruction and makes the filter design direct.

FIR filters are often used because of their linear-phase response. However, there are certain applications where the linear-phase property is not required, such as signal energy estimation, but IIR filters can not be used due to the limitation of sample rate imposed by the recursive algorithm. In this work, we discuss multiplierless implementation of minimum order, and therefore nonlinear-phase, FIR filters and compare it to the linear-phase counterpart.

When hardware for implementing elementary functions is discussed it is often stated that for "small enough" tables it is possible to just synthesize the HDL description to standard cells. In this work we investigate this fact and show that the resulting cell area primarily depends on the smallest of the number of input and output bits, while the contribution of the larger of the two bit-widths is significantly smaller.

In this work we present the design and implementation of a decimation filter for an audio range AE-modulator. The architecture is based on a dual wordlength multiply-accumulate (MAC) unit to handle the reduced wordlength of the input. Each stage is composed of FIR filters which are mapped to the MAC unit. The design trade-offs and decisions for co-design of architecture and filters are discussed.

In this work we propose a switching activity model for single adder multipliers. This correspond to the case where a signal is added to a shifted version of itself, which is a common part in multiple constant multiplication (MCM). Hence, the proposed model is suitable to be used in power consumption aware MCM algorithms. The model is shown to agree well with simulations, and for the studied test cases a maximum error of 0.26% is obtained.

The rising demand for portable system is increasing the importance of low power as a design consideration. In this sense, leakage power is increasing much faster than dynamic power at smaller dimensions. Peak values of supply current are related to noise injected into the substrate and/or propagated through supply network, limiting the performances of the sensitive analog and RF portions of mixed-signal circuits. This paper analyses how these three aspects, dynamic power, leakage power and peak power, can be considered together, optimizing the sizing and design of basic cells, with a reduced degradation in performances. The suited sizing of basic cells, show the benefits of the proposed technique, validated through simulation results on 130 nm nand, nor and inverter cells.

In this paper, alow-complexity approach to implement a class of flexible frequency-band reallocation (FFBR) multi-input multi-output (MIMO) networks, which use variable oversampled complex-modulated filter banks, is introduced. Two alternatives in processing real signals using real input/output and complex input/output FFBR networks (or simply, real and complex FFBR networks, respectively) are considered. It is shown that to process each sample, the real case requires less number of real operations compared to its complex counterpart. Furthermore, the real case has a smaller growth rate in the number of real operations with respect to the prototype filter order. In addition, the real FFBR network eliminates the need for two Hilbert transformers whereas in the complex FFBR case, to achieve high efficiency in FBR, there is a need for high-order Hilbert transformers.

In this paper, we introduce a non-uniform transmultiplexer capable of generating arbitrary-bandwidth user signals. The transmultiplexer consists of linear-phase finite-length impulse response (FIR) filters and Farrow structures for arbitrary-rate interpolation/decimation. By applying the FIR rational sampling rate conversion (SRC) equivalent of the Farrow structure, we model the behavior of the multiplexer and derive the conditions under which the system can approximate perfect reconstruction. Futhermore, we illustrate the functionality of the proposed transmultiplexer and we analyze the performance and functionality of a flexible frequency-band reallocation (FFBR) network using this transmultiplexer.

In this paper, we show that circulator-tree wave digital filters are an interesting alternative to lattice WDFs. Furthermore, we provide two simple programs for design of lattice and circulator-tree lowpass filters and compare the two structures with respect to element sensitivity.

Implementation of FIR filters using shift-and-add multipliers has been an active research area for the last decade. However, almost all algorithms so far has been focused on reducing the number of adders and subtractors, while little effort was put on the bit-level implementation. In this work we propose a method to optimize the number of full adders and half adders required to realize a given number of additions. We present results which show that both area and power consumption can be reduced using the proposed method.

When designing thereduction tree of a parallel multiplier, we can exploit a largeintrinsic freedom for the interconnection order of partialproducts. The transition activities vary significantly fordifferent internal partial products. In this work we propose amethod for generation of power-efficient parallel multipliers insuch a way that its partial products are connected to minimizeactivity. The reduction tree is designed progressively. A SimulatedAnnealing optimizer uses power cost numbers from a speciallyimplemented probabilistic gate-level power estimator and selects apower-efficient solution for each stage of the reduction tree. VHDLsimulation using ModelSim shows a significant reduction in theoverall number of transitions. This reduction ranges from 15% up to32% compared to randomly generated reduction trees and is achievedwithout any noticeable area or performanceoverhead.

In this work we focus on reducing the simultaneous switching noise located in the frequency band from DC up to half of the digital clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. We use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 mum CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB when using the proposed method. The cost is an increase in power consumption of almost a factor of three and a higher transistor count.

Computations in logarithmic number systems require realizations of four different elementary functions. In this work we utilize a recently proposed approximation method based on weighted sums of bit-products to realize these functions. It is shown that the considered method can be used to efficiently realize the different functions. However, a transformation is proposed to improve the results for functions with logarithmic characteristics.

This paper provides error analysis regarding filter approximation errors versus estimation errors when utilizing Farrowbased fractional-delay filters for time-delay estimation. Further, a new technique is introduced which works on batches of samples and utilizes the Newton-Raphson technique for finding the minimum of the corresponding cost function.

Multiple constant multiplication (MCM), i.e., realizing a number of constant multiplications using a minimum number of adders and subtracters, has been an active research area for the last decade. Almost all work has been focused on single rate FIR filters. However, for polyphase interpolation and decimation FIR filters there are two different implementation alternatives. For interpolation, direct form subfilters lead to fewer registers as they can be shared among the subfilters. The arithmetic part corresponds to a matrix vector multiplication. Using transposed direct form subfilters, the registers can not be shared, while the arithmetic part has the same input to all coefficients, and, hence, the redundancy between the coefficients is expected to be higher. For decimation filters the opposite holds for direct form and transposed direct form subfilters. In this work we discuss the trade-off between adders/subtracters and registers, and present implementation results for area, speed, and power for different realizations

In this work a novel approach for approximating elementary functions is presented. By rewriting the function as a sum of weighted bit-products an efficient implementation is obtained. For most functions a majority of the bit-products can be neglected and still obtain good accuracy. The method is suitable for high-speed implementation of fixed-point functions.

This paper introduces multivariate polynomial impulse response time-varying FIR filters for reconstruction of M-periodic nonuniformly sampled signals. The main advantages of these reconstruction filters are that 1) they do not require on-line filter design, and 2) most of their multipliers are fixed and can thus be implemented using low-cost dedicated multiplier elements. This is in contrast to existing filters that require on-line design as well as many general multipliers in the implementation. By using the proposed filters, the overall implementation cost may therefore be reduced in applications where the sampling pattern changes now and then. Design examples are included demonstrating the usefulness of the proposed filters.

In this paper we examine the relation between signal-to-noise-ratio, oversampling ratio, transition bandwidth, and filter order for some commonly used sigma-delta-modulators and corresponding decimation filters. The decimation filters are equi-ripple finite impulse response filters and it is demonstrated that, for any given filter order, there exists an optimum choice of the stopband ripple and stopband edge which minimizes the signal-to-noise-ratio degradation.

This paper introduces polynomial impulse response time-varying FIR filters for reconstruction of two-periodic nonuniformly sampled signals. The main advantages of using these reconstruction filters are that on-line filter design is avoided, and filters with fixed dedicated multipliers can be used in an implementation (except for a few general multipliers). This is in contrast to existing filters that require on-line design as well as general multipliers in the implementation. By using the proposed filters, the overall implementation cost can therefore be reduced dramatically in applications where the sampling pattern changes now and then.

In this work a digital filter is placed on the same chip as an analog filter. We investigate how the simultaneous switching noise is propagated from the digital filter to different nodes on a manufactured chip. Conventional substrate noise reduction methods are used, e.g., separate power supplies, guard rings, and multiple pins for power supplies. We also investigate if the effect of substrate noise on the analog filter can be reduced by using a noise reduction method, which use long rise and fall times of the digital clock. The measured noise on the output of the analog filter was reduced by 30% up to 50% when the method was used.

In this work, circuits for on-chip measurement and periodic waveform capture are designed. The aim is to analyze disturbances in mixed-signal chips such as simultaneous switching noise and the transfer of substrate noise. A programmable reference generator that replaces the standard digital-to-analog converter is proposed. It is based on a resistor string that is connected in a circular structure. A feature is that the reference outputs to the different comparators in the measurement channels are distributed over the nodes of the resistor string. Comparing with using a complete digital-to-analog converter, the use of a buffer is avoided. Hence, there is a potential reduction in the parasitic capacitance and power consumption as well as an increase in speed. We present results from a test chip demonstrating that simultaneous switching noise can be measured with the presented approach.

One of the major contributors to the static nonlinearity of a current-steering digital-to-analog converter (DAC) is mismatch between current sources. A technique for enhancing the yield of binary-weighted current-steering DACs is proposed. The technique utilizes a special case of a general technique for spectral shaping of DAC nonlinearity errors presented earlier and requires oversampling. The technique relies on two DAC models with low computational complexity that can be integrated with the DAC at a negligible cost in terms of area and power consumption. Behavioral-level simulation results indicate that the proposed method has a good potential of enhancing the yield of binary-weighted DACs for situations where the matching errors constitute the dominating source of nonlinearity.

Simultaneous switching noise (SSN) can degrade the performance of digital circuits. In mixed-signal circuits, the performance of analog circuits are degraded by the SSN that is spread from digital circuits through the substrate to the analog circuits. The most critical parameter when considering SSN is the parasitic inductance in the power supply path from off-chip to on-chip. In this paper, basic theories of inductance of current paths are given for parallel interconnects throughout examples. The results from these examples show that the placement of interconnects plays a big role for the effective inductance. Power supply interconnects should be placed with small distances in between, and so that currents in adjacent interconnects are in opposite directions. With this strategy, a low inductance in the power supply current path can be achieved. The importance of choosing a good package for the silicon die is also briefly discussed.

In this work amodel for estimation of the switching activity in ripple-carryadders is presented. The model is based on word-level statistics,such as mean, variance, and correlation, of the two input signalsto be added. It is shown that the proposed model gives accurateresults when the two-s-complement represented inputs are realworld signals.

In this work a novel architecture suitable for high-speed FIR decimation filters for single-bit sigma-delta modulation is proposed. By using efficient data and coefficient representation the total number of partial products is reduced leading to low power consumption. The work is focused on filters designed based on cascaded comb filters, although the approach is applicable to any FIR filter.

Recently, a novel technique to compute sine and cosine has been proposed. By rewriting the expressions using trigonometric equations a weighted sum of bit-products is used to compute the values. This can then be mapped onto a bit-product generator followed by an adder tree. This provides an efficient architecture that can be pipelined to an arbitrary degree. It was shown in previous work that it is possible to remove a large portion of the bit-products and still obtain accurate results. The objective of this work is to study the effects of this removal and also the finite wordlength representation of the weights. Furthermore, optimization problems are formulated that can be used to minimize the maximum absolute error, the average absolute error, and the mean square error for the output values, respectively, as well as implementation complexity under error constraints.

Recently, a noveltechnique to compute sine and cosine has been proposed. Byrewriting the expressions using trigonometric equations a weightedsum of bit-products are used to compute the values. This can thenbe mapped onto a bit-product generator followed by an adder tree.This provides an efficient architecture that can be pipelined to anarbitrary degree. It was shown in previous work that it is possibleto remove a large portion of the bit-products and still obtainaccurate results. The effects of this removal and also the finiteworldlength representation of the weights has also been discussedin previous work. The objective of this work is to study differentways to split the architecture into sub-blocks that may be disabledto decrease the power consumption.

Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we propose an architecture for an early decision decoding algorithm. The algorithm significantly reduces the number of memory accesses. Simulation results show that the increased energy dissipation of the components is small compared to the reduced dissipation of the memories.

The purpose of this work is to investigate the possibility to implement analog base band circuitry along with digital circuitry in silicon-on-insulator technology. Hence a 6 bit Nyquist rate flash analog-to-digital converter is designed in a 130 nm CMOS silicon-on-insulator technology. The converter is aimed for read channel or ultra-wideband radio applications. The simulations indicate a 170 mW power consumption at a maximum sampling rate of 1 GHz. The supply voltage is only 1.2 V. The effective number of bit is 5.8 bit and the effective resolution bandwidth is 390 MHz. An energy per conversion step of 3.9 pJ indicate that this converter is as efficient as other state-of-the-art converters, without using interpolation or averaging techniques.

The purpose of this work is to find good design techniques for the analog/mixed-signal parts of a system-onchip in SOI. A comparator has therefore been designed and manufactured in a 0.13 um partially depleted SOI CMOS technology. The comparator is a first step towards the design of a complete 6-bit flash analog-to-digital converter, with a sampling frequency of 1.5 GHz, or above. An introduction to the silicon-on-insulator (SOI) technology is also given and some of the major advantages and disadvantages of using SOI are presented.

Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we investigate a modification to the decoding algorithm, using early decisions for bits with high reliabilities. This reduces the amount of messages passed by the algorithm, which can be expected to reduce the switching activity of a hardware implementation. While direct application of the modification results in severe performance penalties, we show how to adapt the algorithm to reduce the impact, resulting in a negligible decrease in error correction performance.

Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we investigate a modification to the decoding algorithm, using early decisions for bits with high reliabilities. Currently, there are two early decision schemes proposed. We compare their theoretical performances and their suitability for hardware implementation. We also propose a new decision method, which we call weak decisions, that offers an increase in performance by a factor of two.

An important issue in the next-generation satellite-based communication systems is the satellite on-board reallocation of information which calls for digital flexible frequency-band reallocation (FFBR) networks. This paper introduces a new class of FFBR networks based on variable oversampled complex-modulated filter banks (FBs). The new class can outperform previously existing ones when flexibility, low complexity and inherent parallelism, perfect frequency-band reallocation, and simplicity are considered simultaneously.

In this work, we study how retiming can be used to reduce glitches in digit-serial recursive filters. It is a well known fact that glitches can make up a large portion of the dynamic power consumption in digital systems. Digit-serial recursive systems contain registers that can be retimed to reduce the amount of glitches. A second-order digit-serial LDI allpass filter has been implemented to verify this statement. It is shown that retiming can reduce the power consumption with about 20% for small digit-sizes without affecting the throughput of the filter. We also show that introducing a large number of registers in the filter structure will increase the current consumption. This trade-off, between reducing the amount of glitches and the increase in the number of registers, is also considered in this work.

In this paper, we propose a VLSI implementation method for one-dimensional discrete wavelet transform (1D-DWT) filter bank based on the GALS systems approach. An asynchronous wrapper, which includes two data communication ports and a local clock controller, is designed for the asynchronous data communication between the locally synchronous filtering modules in the wavelet filter bank. The detailed design methodology for the GALS architecture of ID-DWT filter bank is presented, and the circuits are validated with VHDL and implemented with standard CMOS technology.

In this paper, performance trade-offs between throughput, and energy consumption, in implementation of recursive digital filters are presented. Digit-serial arithmetic with different degree of pipelining are used in the implementions. As a demonstration object, a bireciprocal third-order lattice wave digital filter is used. Simulations with HSPICE show that a maximum throughput is obtained using pipelined processing elements with a digit-size equal to the fractional bits in the filter coefficient. The use of non-pipelined processing elements yields minimum energy consumption. A trade-off between throughput and energy consumption can be made by pipelining only some of the processing elements.

A flash analog-to-digital converter is proposed that employs a new dynamic element matching architecture. The architecture uses a new strategy of incorporating switches in the voltage reference generator that allows lower hardware complexity and higher conversion speed than comparable converters. The converter has been modeled and simulated on a behavioral level in Matlab. The results indicate good linearity properties that together with the expected speed performance should make it suitable in intended communications applications.

In this work a model for estimation of the power consumption in bit-serial, constant coefficient multipliers is presented. The multipliers are implemented using shift-add operations. Model parameters for the required components, i.e., flip-flops and full-adders, are derived. The power for a multiplier is obtained by summing the power for all components included in the corresponding network of shifts and adders.

In this work a mixed integer linear programming (MILP) formulation for the design of a class of linear-phase FIR filters are presented. The formulation can be solved using general purpose MILP solvers to obtain filter implementationwith a minimum number of signed-power-of-two (SPT) terms given a filter specification. The filter structures considered are based on reduced complexity polyphase decomposition. It is shown that the total number of SPT terms per sample can be reduced using this filter architecture. However, the savings are not as large as other work propose, when optimal design techniques are used.

In this paper we propose a method for implementation of multiple constant multiplications, as used in, for example, FIR filters. The method is shifted difference coefficient method where the differences are selected using a minimum spanning tree. By finding a minimum spanning tree of an undirected graph, corresponding to the coefficients, an implementation of a multiple constant multiplication block with low arithmetic complexity is obtained. There are algorithms that find a minimum spanning tree in polynomial time, making the proposed method computational efficient. We also propose that the differences are computed on odd coefficients only. This reduces the number of adders in an implementation further, compared to other difference coefficient methods. Several stages of differences, i.e., a set of differences is used to compute a new set of higher order differences, may also be used. We show that the proposed method give optimal, or close to optimal, results with respect to the number of additions required for a number of FIR filter implementations.

Fixed coefficient digit-serial/parallel multipliers are presented. The multipliers are based on unfolded bit-serial/parallel multipliers in combination with canonic signed-digit coding of the fixed coefficient. The unfolding yields long critical paths, which cannot be pipelined due to the feed back carry loops, and carry-look-ahead techniques cannot be applied efficiently since the propagating sum path will increase. By using canonic signed-digit code the multiplier gains higher throughput and lower latency since the critical path is reduced without pipelining. Hence, the throughput is increased with between 56 and 150 percent compared with two's complement coded coefficients, and for the digit-sizes {2,3,4} it has the same throughput as the corresponding digit-serial adder.

In this paper, we present a new digit-serial hybrid adder. The adder can be pipelined to the bit-level and is, therefore, well suited for high-speed applications. The main advantage of the proposed adder is that it can be implemented with few pipelining stages. We compare speed, area, and power consumption for the proposed adder with a digit-serial carry-look-ahead adder and a digit-serial Ladner-Fisher adder. The results show that the delay of the digit-serial hybrid adder is lower than the others studied in this paper for digit-sizes up to d=12. For these digit-sizes the digit-serial hybrid adder has on average 17% smaller critical path than the digit-serial carry-look-ahead adder and a 21% smaller critical path that the digit-serial Ladner-Fisher adder.